User Manual

52
T89C51AC2
Rev. B – 19-Dec-01
Figure 22. T im er/Counter x (x = 0 or 1) in Mode 0
12.2.2 M ode 1 (16-bit Timer) Mode 1 configure s Timer 0 a s a 16-bit Tim er with TH0 and TL0 regist ers connect ed in
cascade (see Figure 23). T he selected input i nc rements TL0 register.
Figure 23. T im er/Counter x (x = 0 or 1) in Mode 1
12.2.3 Mode 2 (8-bit Tim er with
Auto-Reload)
Mode 2 configures Timer 0 as an 8-bit Timer (TL0 register) that automatically reloads
from TH0 register (see Figure 24). TL0 overflow sets TF0 flag in TCON register and
reloads TL0 with the contents of TH0, w hich is preset by software. When the interrupt
reques t is serviced, hardware clears TF 0. The reload leaves TH0 unc hanged. The nex t
reload value ma y be changed at any time by writing it to TH0 register.
Figure 24. T im er/Counter x (x = 0 or 1) in Mode 2
FTx
CLOCK
TRx
TCON reg
TFx
TCON reg
0
1
GATEx
TMOD reg
÷ 6
Overflow
Timer x
Interrupt
Request
C/Tx#
TMOD reg
TLx
(5 bits)
THx
(8 bits)
INTx#
Tx
see section “Clock”
TRx
TCON reg
TFx
TCON reg
0
1
GATEx
TMOD reg
Overflow
Timer x
Interrupt
Request
C/Tx#
TMOD reg
TLx
(8 bits)
THx
(8 bits)
INTx#
Tx
FTx
CLOCK
÷ 6
see section “ Clock”
TRx
TCON reg
TFx
TCON reg
0
1
GATEx
TMOD reg
Overflow
Timer x
Interrupt
Request
C/Tx#
TMOD reg
TLx
(8 bits)
THx
(8 bits)
INTx#
Tx
FTx
CLOCK
÷ 6
see section “ Clock”