User Manual

45
T89C51AC2
Rev. B – 19-Dec-01
11. Serial I/O Port The T89C51AC 2 I/ O serial port is compa tible with the I/O serial port in t he 80C52.
It prov ides bot h sy nch ronous and asy nc hronous co mm unication modes. It operates as a
Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes
(Modes 1, 2 and 3). As y nc hronous transmission and rec eption ca n oc c ur simul tan eously
and at different baud rates
Serial I/O port includ es the following enhanc ements:
• Fram ing error detection
• Automatic address recognition
Figure 18. Serial I/O P ort Block Diagram
11.1 Framing Error
Detection
Frami ng bit error detection is provided for t he three asynchronous modes. To enable the
framing bit error detec tion feat ure, s et S MOD0 bit in PCO N register.
Figure 19. Framing Error Block Diagra m
W hen this feature is enabl ed, the rec eiver chec ks each incom ing data f rame for a valid
stop bit. An invalid stop bit m ay re su lt from noise on the serial lines or from simultaneous
transmissio n by t w o CPUs . I f a valid s top bit is n ot f ound, the Frami ng Error bit (FE) in
SCON register bit is set.
The software may exam ine the F E bit af ter eac h reception to chec k f or data errors.
Onc e set, only software or a reset clears the FE bit. S ubs equent ly received fram es with
Write SBUF
RI
TI
SBUF
Transmitter
SBUF
Receiver
IB Bus
Mode0Transmit
Receive
Shift register
Load SBUF
Read S BUF
Interrupt Request
Serial Port
TXD
RXD
RITIRB8TB8RENSM2SM1SM0/FE
IDLPDGF0GF1POF-SMOD0SMOD1
To UART fr aming error control
SM0toUARTmodecontrol
Set FE bit if stop bit is 0 (framing error)