User Manual

106
T89C51AC2
Rev. B – 19-Dec-01
18.5.14 F lash Memory Table 69. Tim ing Symbol Definitions
Table 70. Memory AC Timing
VDD= 5 V + /- 10% , TA= -40 to +85°C
Figure 45. F LA SH Mem ory - I S P Wave forms
Figure 46. F LA SH Mem ory - Int ernal Busy Wavef orms
Signals Conditions
S(Hardware
condition)
PSEN#,EA L Low
RRST VValid
B FBUSY flag X No Longer Valid
Symbol Parameter Min Typ Max Unit
T
SVRL
Input PSEN# Valid to RST Edge 50 ns
T
RLSX
Input PSEN# Hold after RST Edge 50 ns
T
BHBL
FLASH Internal Busy (Programming) Time 10 ms
RST
T
SVRL
PSEN#1
T
RLSX
FBUSY bit
T
BHBL