Owner's manual

A/T8xC5121

4164G–SCR–07/06

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Table 47. Synthesis of Transfer Protection Mechanisms

Notes: 1. The transfer of SSB Byte is also secured by CRC as the CRC is computed on all the

16K data.

2. If a Bad transfer has occurred in the Internal EEPROM (CRC is bad), as the CRC

check is finally done at the end of CRAM programming, application program will NOT

be executed after any Reset.

Read/Write Protection

Lock Byte In order to protect the content of the internal EEPROM, a Software Security Byte (SSB)

defines two security levels:

• level 0: SSB = 0xFF: Write and Read are allowed

• level 1: SSB = 0xFE: Write is disabled

• level 2: SSB = 0xFC: Write and Read are disabled

This SSB Byte is located at address 3FFDh.

When the level 2 is set, the command to set level 1 is disabled. The security levels can

only be increased.

Source Target Check

MCU CRAM

CRC computed during CRAM Write operation: if error an error code is applied

on P3.7 and Code execution by LJMP000 is not done.

Intern. EEP MCU This Read operation is secured by the Write sequence described above

MCU Intern. EEP

Same protection as in first row above because CRAM is written in sequence

after each page programming of EEP

Ext. EEP MCU Same as above as data are transferred to EEP INT and then to CRAM