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A/T8xC5121
4164G–SCR–07/06
Table 43. AUXR1 Register
AUXR1 - Dual Pointer Selection Register (A2h)
Reset value = XXXX XXX0b
76543210
-------DPS
Bit
Number
Bit
Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
1-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
0DPS
Data pointer 1
Clear to select DPTR0 as Data Pointer.
Set to select DPTR1 as Data Pointer.