Owner's manual

22
A/T8xC5121
4164G–SCR–07/06
Clock Management In order to optimize the power consumption and the execution time needed for a specific
task, an internal prescaler feature and a X2 feature have been implemented between
the oscillator and the CPU.
Functional Block
Diagram
Figure 11. Clock Generation Diagram
If CKRL<>7 then:
If CKRL = 7 then:
CKRL Prescalor Factor
71
62
54
46
38
210
112
014
1
2
F
OSC
1
2(7-CKRL)
CKRL = 7
X2
F
CLK_Periph
F
CLK_CPU
CKCON0
CKRL
F
OSC
2
x2
0
1
0
1
Osc.
XTAL1
XTAL2
F
CLK CPU
F
OSC
2
x2()
-----------------
1
2 7 CKRL
()
-----------------------------------=
F
CLK CPU
Fosc
2
x2
--------------=