Features • 80C51 Core • • • • • • • • • • • • • • • • • • • – 12 or 6 Clocks per Instruction (X1 and X2 Modes) – 256 Bytes Scratchpad RAM – Dual Data Pointer – Two 16-bit Timer/Counters: T0 and T1 T83C5121 with 16 Kbytes Mask ROM T85C5121 with 16 Kbytes Code RAM T89C5121 with 16 Kbytes Code RAM and 16 Kbytes EEPROM On-chip Expanded RAM (XRAM): 256 Bytes Versatile Host Serial Interface – Full-duplex Enhanced UART (EUART) with Dedicated Baud Rate Generator (BRG): Most Standard Speeds up to 230K bits/s a
Description T8xC5121 is a high performance CMOS ROM/CRAM derivative of the 80C51 CMOS single chip 8-bit microcontrollers. T8xC5121 retains the features of the Atmel 80C51 with extended ROM capacity (16 Kbytes), 512 bytes of internal RAM, a 4-level interrupt system, two 16-bit timer/counters (T0/T1), a full duplex enhanced UART (EUART) with baud rate generator (BRG) and an on-chip oscillator.
A/T8xC5121 Pin Description Figure 2. 24-pin SSOP Pinout CVSS 1 24 VCC LI 2 EV CC CVCC 3 4 23 22 P1.5/CRST P1.4/CCLK 21 20 19 18 5 DVCC VSS P3.0/RxD P1.3/CC4 6 P1.2/CPRES P1.1/CC8 P1.0/CIO RST 7 8 17 P3.3/INT1/OE P3.4/T0 9 16 P3.2/INT0 10 15 14 P3.5/CIO1/T1 13 P3.7/CRST1/LED1 XTAL2 11 12 XTAL1 P3.1/TxD P3.6/CCLK1/LED0 N/C Vcc EVcc DVcc CVss N/C N/C LI Figure 3. QFN32 Pinout 32 31 30 29 28 27 26 25 CVcc P1.5/CRST P1.4/CCLK P1.3/CC4 P1.2/CPRES P1.1/CC8 P1.
7 NC NC NC NC EVCC NC CVSS VCC LI NC NC CVCC P1.5/CRST Figure 4. PLCC52 Pinout 6 5 4 3 2 1 52 51 50 49 48 47 8 9 46 45 10 44 11 43 P2.7/A15 12 13 P2.6/A14 14 42 41 40 P2.5/A13 15 16 39 38 P0.3/AD3 P0.6/AD6 17 37 P3.3/INT1/OE 18 36 P3.4/T0 19 20 35 P3.2/INT0 P3.5/CIO1/T1 P1.4/CCLK P1.3/CC4 EA PSEN ALE P1.2/CPRES P1.1/CC8 P1.0/CIO P2.4/A12 RST 34 DV CC VSS P3.0/RxD P3.1/TxD P0.0/AD0 P0.1/AD1 P0.2/AD2 4 P0.4/AD4 P3.6/CCLK1/LED0 P3.7/CRST1/LED1 P0.7/AD7 P2.
A/T8xC5121 Signals All the T8xC5121 signals are detailed in Table 1. The port structure is described in Section “Port Structure Description”. Table 1. Ports Description Internal Port Signal Name P1.0 CIO Power Alternate Supply ESD Type CVCC 4 kV I/O I/O I P1.1 CC8 CVCC 4 kV O O I P1.2 CPRES VCC 4 kV I Description Smart card interface function Card I/O. Input/Output function P1.0 is a bi-directional I/O port . Reset configuration Input .
Table 1. Ports Description (Continued) Internal Port Signal Name P3.0 RxD Power Alternate Supply EVCC ESD Type I I/O I Description UART function Receive data input Input/Output function P3.0 is a bi-directional I/O port with internal pull-ups. Reset configuration Input (high level) UART function P3.1 TxD EVCC O Transmit data output OE active at low or high level depending of PMSOEN bits in SIOCON Reg. I/O Z Input/Output function P3.1 is a bi-directional I/O port with internal pull-ups.
A/T8xC5121 Table 1. Ports Description (Continued) Internal Port Signal Name Power Alternate Supply ESD Type I/O Description Input/Output function P3.4 is a bi-directional I/O port with internal pull-ups. Timer 0 function: External clock input I When Timer 0 operates as a counter, a falling edge on the T0 pin increments the count. Z P3.5 CIO1 DVCC I/O I/O Reset configuration High impedance due to PMOS switched OFF Alternate card function Card I/O Input/Output function P3.
Table 1. Ports Description (Continued) Internal Port Signal Name Power Alternate RST Supply VCC ESD Type Description I/O Reset input Holding this pin low for 64 oscillator periods while the oscillator is running resets the device. The Port pins are driven to their reset conditions when a voltage lower than VIL is applied, whether or not the oscillator is running. This pin has an internal pull-up resistor which allows the device to be reset by connecting a capacitor between this pin and VSS.
A/T8xC5121 Table 1. Ports Description (Continued) Internal Port Signal Name Power Alternate Supply ESD Type Description ONLY FOR PLCC52 version P0[7:0] AD[7:0] VCC I/O Input/Output function Port 0 P0 is an 8-bit open-drain bi-directional I/O port. Port 0 pins that have 1s written to them float and can be used as high impedance inputs. To avoid any parasitic current consumption, Floating P0 inputs must be pulled to VCC or VSS.
Port Structure Description The different ports structures are described as follows. Quasi Bi-directional Output Configuration The default port output configuration for standard I/O ports is the quasi bi-directional output that is common on the 80C51 and most of its derivatives. This output type can be used as both an input and output without the need to reconfigure the port. This is possible because when the port outputs a logic high, it is weakly driven, allowing an external device to pull the pin low.
A/T8xC5121 Figure 6. Push-pull Output Configuration P Strong PMOS Pin Port latch Data N NMOS Input Data LED Output Configuration The input only configuration is shown in Figure 7. Figure 7. LED Source Current Configuration P P 2 CPU CLOCK DELAY PMOS Strong P Weak Medium Pin NMOS LEDx.0 LED1CTRL Port Latch Data LEDx.
SFR Mapping 12 The Special Function Registers (SFR) of the T8xC5121 belongs to the following categories: • C51 core registers: ACC, B, DPH, DPL, PSW, SP • I/O port registers: P0, P1, P2, P3 • Timer 0 registers: TCON, TH0, TH1, TMOD, TL0, TL1 • Serial I/O port registers: SADDR, SADEN, SBUF, SCON, BRL, BDRCON • Power and clock control registers: PCON, CKRL, CKCON0, CKCON1, DCCKPS • Interrupt system registers: IE0, IPL0, IPH0, IE1,IPL1, IPH1, ISEL • Watchdog Timer 0: WDTRST, WDTPRG • Others: A
A/T8xC5121 Table 2.
PowerMonitor The PowerMonitor function supervises the evolution of the voltages feeding the microcontroller, and if needed, suspends its activity when the detected value is out of specification. It is guaranteed to start up properly when T8xC5121 is powered up and prevents code execution errors when the power supply becomes lower than the functional threshold. This section describes the functions of the PowerMonitor.
A/T8xC5121 Figure 9. Power-Up and Steady-state Conditions Monitored DVCC VPFDP VPFDM tG Steady-state Condition Power-down Power-up trise tfall Reset VCC Such device when it is integrated in a microcontroller, forces the CPU in reset mode when VDD reaches a voltage condition which is out of the specification. The thresholds and their functions are: • VPFDP: the output voltage of the regulator has reached a minimum functional value at the power-up. The circuit leaves the RESET mode.
Power Monitoring and Clock Management Idle Mode For applications where power consumption is a critical factor, three power modes are provided: • Idle mode • Power-down mode • Clock Management (X2 feature and Clock Prescaler) • 3V Regulator Modes (pulsed or not pulsed) An instruction that sets PCON.0 causes the last instruction to be executed before going into the Idle mode.
A/T8xC5121 The ports status under Power-down is the status which was valid before entering this mode. The INT1 interrupt is a multiplexed input (see Interrupt paragraph) with CPRES (Card detection) and Rxd (UART Rx). So these three inputs can be used to exit from Powerdown mode. The configurations which must be set are detailed below: • • Rxd input: – RXEN (ISEL.0) must be set – EX1 (IE0.
Reduced EMI Mode The ALE signal is used to demultiplex address and data buses on port 0 when used with external program or data memory. Nevertheless, during internal code execution, ALE signal is still generated. Only in case of PLCC52 version, in order to reduce EMI, ALE signal can be disabled by setting AO bit. The AO bit is located in AUXR register at bit location 0 (See Table 4). As soon as AO is set, ALE is no longer output but remains active during MOVX and MOVC instructions and external fetches.
A/T8xC5121 Table 4. AUXR Register AUXR (S:8Eh) Auxiliary Register 7 6 5 4 3 2 1 0 - LP - - - - EXTRAM AO Bit Bit Number Mnemonic 7 - 6 LP Description Reserved The value read from this bit is indeterminate. Do not set this bit. Low Power mode selection Clear to select standard mode Set to select low consumption mode 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit.
Table 5. IE0 Register IE0 Interrupt Enable Register (A8h) 7 6 5 4 3 2 1 0 EA - - ES ET1 EX1 ET0 EX0 Bit Bit Number Mnemonic Description Enable All interrupt bit Clear to disable all interrupts. Set to enable all interrupts. If EA = 1, each interrupt source is individually enabled or disabled by setting or clearing its interrupt enable bit. 7 EA 6 - Reserved The value read from this bit is indeterminate. Do not set this bit.
A/T8xC5121 Table 6. ISEL Register ISEL (S:BAh) Interrupt Enable Register 7 6 5 4 3 2 1 0 CPLEV - RXIT PRESIT OELEV OEEN RXEN PRESEN Bit Bit Number Mnemonic Description Card presence detection level 7 CPLEV This bit indicates which CPRES level will bring about an interrupt Set this bit to indicate that Card Presence IT will appear if CPRES is at high level. Clear this bit to indicate that Card Presence IT will appear if CPRES is at low level.
Clock Management In order to optimize the power consumption and the execution time needed for a specific task, an internal prescaler feature and a X2 feature have been implemented between the oscillator and the CPU. Functional Block Diagram Figure 11. Clock Generation Diagram 1 2(7-CKRL) XTAL1 FOSC Osc.
A/T8xC5121 X2 Feature The T8xC5121 core needs only 6 clock periods per machine cycle. This feature called ”X2” provides the following advantages: • Divides frequency crystals by 2 (cheaper crystals) while keeping same CPU power. • Saves power consumption while keeping same CPU power (oscillator power saving). • Saves power consumption by dynamically dividing the operating frequency by 2 in operating and idle modes. • Increases CPU power by 2 while keeping same crystal frequency.
Clock Prescaler Before supplying the CPU and the peripherals, the main clock is divided by a factor 2 to 30 to reduce the CPU power consumption. This factor is controlled with the CKRL register. Table 7.
A/T8xC5121 Table 9. CKCON0 Register CKCON0 - Clock Control Register (8Fh) 7 6 5 4 3 2 1 0 - WDX2 - SIX2 - T1X2 T0X2 X2 Bit Bit Number Mnemonic 7 - Description Reserved Watchdog clock 6 WDX2 (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect) Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.
Table 10. CKCON1 Register CKCON1 - Clock Control Register (AFh) 7 6 5 4 3 2 1 0 - - - - SCX2 - - - Bit Bit Number Mnemonic 7 - Reserved 6 - Reserved 5 - Reserved 4 - Reserved 3 SCX2 Description SCIB clock Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.
A/T8xC5121 DC/DC Clock The DC/DC block needs a clock with a 50% duty cycle. The frequency must also respect a value between 3.68 MHz and 4 MHz. The first requirement imposes a divider in the clock path and the second constraint is solved with the use of a prescaler. Figure 13. Functional Block Diagram 1 FOSC (2 to 5) FCLK_DC/DC FOSC 2 to 5 DCCKPS Address BFh Clock Control Register This register is used to reload the clock prescaler of the DC/DC converter clock. Table 11.
A/T8xC5121 4164G–SCR–07/06
A/T8xC5121 Smart Card Interface Block (SCIB) Introduction The SCIB provides all signals to directly interface a smart card. Compliance with the ISO7816, EMV’2000, GSM and WHQL standards has been certified. Both synchronous (e.g. memory card) and asynchronous smart cards (e.g. microprocessor card) are supported. The component supplies the different voltages requested by the smart card. The power-off sequence is directly managed by the SCIB.
Block Diagram The Smart Card Interface Block diagram is shown in Figure 14. Figure 14. SCIB Block Diagram Barrel shifter IO (in) IO (out) Clk_iso CLK Clk_cpu Etu counter Guard time counter I/O mux Scart fsm RST C4 (out) Waiting time counter C8 (out) CLK1 C4 (in) SCI Registers C8 (in) INT Interrupt generator Power on Power off VCARD fsm Functional Description The architecture of the Smart Card Interface Block is detailed below.
A/T8xC5121 the different counters. One of the most important counters is the guard time counter that gives time slots corresponding to the character frame. It is enabled only in UART mode. The transition from the receipt mode to the transmit mode is done automatically. Priority is given to the transmission. ETU Counter The ETU (Elementary Timing Unit) counter controls the working frequency of the barrel shifter, in fact, it generates the enable signal of the barrel shifter.
Waiting Time Counter (WT) The WT counter is a 24 bits down counter which can be loaded with the value contained in the SCWT2, SCWT1, SCWT0 registers. Its main purpose is time out signal generation. It is 24 bits wide and is decremented at the ETU rate. The ETU counter acts as a prescaler (See Figure 16). When the WT counter timeout, an interrupt is generated and the SCIB function is locked: reception and emission are disabled. It can be enabled by resetting the macro or reloading the counter. Figure 16.
A/T8xC5121 Figure 17. T = 0 Mode > GT CHAR 2 CHAR 1 < WT Figure 18. T = 1 Mode Reception Transmission BLOC 2 BLOC 1 CHAR 1 CHAR n CHAR 2 < CWT Power-on and Power-off FSM CHAR n+1 < BWT CHAR n+2 CHAR n+3 < CWT In this state, the machine applies the signals on the smart card in accordance with ISO7816 standard. To be able to power-on the SCIB, the card presence is mandatory. Removal of the smart card will automatically start the power-off sequence as described in Figure 19. Figure 19.
Interrupt Generator There are several sources of interruption but the SCIB macro-cell issues only one interrupt signal: SCIB IT. Figure 20. SCIB Interrupt Sources Transmit buffer copied to shift register Output current out of range Output voltage out of range Timeout on WT counter Complete transmission Complete reception Parity error detected ESCTBI CIccER ECVccER SCIB IT ESCWTI ESCTI ESCRI ESCPI This signal is high level active.
A/T8xC5121 Other Features Clock The Ck-ISO input must be in the range 1 - 5 MHz according to ISO7816. The ISO Clock diagram and the configuration examples are shown in Figure 20. Figure 21. Clock Diagram of the SCIB Block FCLK_CPU FCLK_Periph SCIB Clk_cpu 1 1 Clk_iso 2 F4_8MHz 0 SCX2 Reset value = 1 CKCON 1.3 Table 13.
Figure 22. Alternate Card CVCC CRST CIO CCLK Main card CPRES FCK_IDLE 1, 2, 4 or 8 FCK_IDLE 1 PR3 P3.6 ALTKPS0,1 SCSR Reg. Card Presence Input CCLK1 Alternate card SIM,SAM 0 CARD SCCLK1 SCSR Reg. The internal pull-up on Card Presence input can be disconnected in order to reduce the consumption (CPRESRES, bit 3 in PMOD0). In this case, an external resistor (typically 1 MΩ) must be externally tied to VCC. CPRES input can generate an interrupt (see Interrupt system section).
A/T8xC5121 DC/DC Converter The Smart Card supply voltage (CVCC) is generated by the integrated DC/DC converter. It is controlled by several registers: • The register described in Section “SCICR Register” controls the CVCC voltage with bits CVcc0, CVcc1 • The register described in Section “SCCON Register”, switches ON/OFF the DC/DC converter with bit CARDVCC • After the selection of the card voltage (CVcc[1:0]), the CARVCC bit is used to switch on the DC\DC converter.
Registers Description Table 15. SCICR Register SCICR (S:B6h, SCRS = 1) Smart Card Interface Control Register 7 6 5 4 3 2 1 0 RESET CARDDET CVcc1 CVcc0 UART WTEN CREP CONV Bit Number 7 6 Bit Mnemonic Description RESET CARDDET Reset Set this bit to reset the SCIB and its configuration Card presence detector sense Clear this bit to indicate the card presence detector is opened when no card is inserted (CPRES is high).
A/T8xC5121 Table 16. SCCON Register SCCON (S:ACh, SCRS = 0) Smart Card Contacts Register 7 6 5 4 3 2 1 0 CLK - CARDC8 CARDC4 CARDIO CARDCLK CARDRST CARDVCC Bit Number Bit Mnemonic Description 7 CLK Card Clock Selection Clear this bit to use the CardClk bit (CARDCLK) to drive Card CLK pin. Set this bit to use XTAL signal to drive the Card CLK pin. Note: internal synchronization avoids any glitch on the CLK pin when switching this bit.
Table 17. SCISR Register SCISR (S:ADh, SCRS = 0) Smart Card UART Interface Status Register 7 6 5 4 3 2 1 0 SCTBE CARDIN CIccOVF CVccOK SCWTO SCTC SCRC SCPE Bit Number Bit Mnemonic Description SCTBE SCIB transmit buffer empty This bit is set by hardware when the Transmit Buffer is copied to the transmit shift register of the Smart Card UART. It is cleared by hardware when SCTBUF is written to.
A/T8xC5121 Table 18. SCIIR Register SCIIR (S:AEh, SCRS = 0) Smart Card UART Interrupt Identification Register (read only) 7 6 5 4 3 2 1 0 SCTBI - CIccERR CVccERR SCWTI SCTI SCRI SCPI Bit Number Bit Mnemonic Description 7 SCTBI SCIB transmit buffer interrupt This bit is set by hardware when the Transmit Buffer is copied to the transmit shift register of the Smart Card UART. It is cleared by hardware when this register is read. 6 - Reserved The value read from this bit is indeterminate.
Table 19. SCIER Register SCIER (S:AEh, SCRS = 1) Smart Card UART Interrupt Enable Register 7 6 5 4 3 2 1 0 ESCTBI - CIccER ECVccER ESCWTI ESCTI ESCRI ESCPI Bit Number Bit Mnemonic 7 ESCTBI 6 - 5 CIccER Card Current Error Interrupt Enable Clear this bit to disable the Card Current Error interrupt. Set this bit to enable the Card Current Error interrupt. 4 ECVccER Card Voltage Error Interrupt Enable Clear this bit to disable the Card Voltage Error interrupt.
A/T8xC5121 Table 20.
Table 22. SCRBUF Register SCRBUF (S:AA read-only, SCRS = 1) Smart Card Receive Buffer Register 7 6 5 4 3 2 1 0 – – – – – – – – Bit Number – Bit Mnemonic Description – Provides the byte received from the I/O pin when SCRI is set. Bit ordering on the I/O pin depends on the Convention (see SCICR Register). Reset Value = 0000 0000b Table 23.
A/T8xC5121 Table 24. SCETU0 Register SCETU0 (S:ACh, SCRS = 1) Smart Card ETU Register 0 7 6 5 4 3 2 1 0 ETU7 ETU6 ETU5 ETU4 ETU3 ETU2 ETU1 ETU0 Bit Number 7-0 Bit Mnemonic Description ETU[7:0] ETU LSB The Elementary Time Unit is (ETU[10:0] - 0.5*COMP)/f, where f is the Card CLK frequency. According to ISO7816, ETU[10:0] can be set between 11 and 2047. The default reset value of ETU[10:0] is 372 (F = 372, D = 1). Reset Value = 0111 0100b Table 25.
Table 27. SCWT2 Register SCWT2 (S:B6h, SCRS = 0) Smart Card Character/Block Wait Time Register 2 7 6 5 4 3 2 1 0 WT23 WT22 WT21 WT20 WT19 WT18 WT17 WT16 Bit Number 7-0 Bit Mnemonic Description WT[23:16] Wait Time Byte 2 Used together with WT[15:0] (see SCWT0 Register). Reset Value = 0000 0000b Table 28.
A/T8xC5121 Interrupt System The T8xC5121 has a total of 6 interrupt vectors: four external interrupts (INT0, INT1/OE, CPRES, RxD), two Timer 0 interrupts (Timer 0s 0 and 1), serial port interrupt and Smart Card Interface interrupt. These interrupts are shown in Figure 23. Figure 23. Interrupt Control System IPH0, IPL0 INT0 IE0 EX0 1 ET0 RXEN 0 RXIT Rxd OEEN CPRES 0 3 TCON Reg.
A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt source. If two interrupt requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced.
A/T8xC5121 Table 32. IE0 Register 7 6 5 4 3 2 1 0 EA - - ES ET1 EX1 ET0 EX0 Bit Bit Number Mnemonic Description Enable All interrupt bit Clear to disable all interrupts. Set to enable all interrupts. If EA = 1, each interrupt source is individually enabled or disabled by setting or clearing its interrupt enable bit. 7 EA 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit.
Table 33. IE1 Register 7 6 5 4 3 2 1 0 - - - - ESCI - - - Bit Bit Number Mnemonic 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit. 3 ESCI 2 - Reserved The value read from this bit is indeterminate.
A/T8xC5121 Table 34. TCON Register TCON (S:88h) Timer 0/Counter Control Register 7 6 5 4 3 2 1 0 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Bit Number Bit Mnemonic Description 7 TF1 Timer 1 Overflow flag Cleared by the hardware when processor vectors to interrupt routine. Set by the hardware on Timer 0/Counter overflow when Timer 1 register overflows. 6 TR1 Timer 1 Run Control bit Clear to turn off Timer 0/Counter 1. Set to turn on Timer 0/Counter 1.
Table 35. ISEL Register 7 6 5 4 3 2 1 0 CPLEV OEIT PRESIT RXIT OELEV OEEN PRESEN RXEN Bit Bit Number Mnemonic Description Card presence detection level 7 CPLEV This bit indicates which CPRES level will bring about an interrupt Set this bit to indicate that Card Presence IT will appear if CPRES is at high level. Clear this bit to indicate that Card Presence IT will appear if CPRES is at low level. 6 - 5 PRESIT Reserved The value read from this bit is indeterminate.
A/T8xC5121 Table 36. IPL0 Register 7 6 5 4 3 2 1 0 - - - PSL PT1L PX1L PT0L PX0L Bit Bit Number Mnemonic 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 PSL Serial port Priority bit Refer to PSH for priority level.
Table 37. IPL1 Register 7 6 5 4 3 2 1 0 - - - - PSCIL - - - Bit Bit Number Mnemonic 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit. 3 PSCIL Reserved The value read from this bit is indeterminate.
A/T8xC5121 Table 38. IPH0 Register 7 6 5 4 3 2 1 0 - - - PSH PT1H PX1H PT0H PX0H Bit Bit Number Mnemonic 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit.
Table 39. IPH1 Register 7 6 5 4 3 2 1 0 - - - - PSCIH - - - Bit Bit Number Mnemonic 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit.
A/T8xC5121 LED Ports Configuration The current source of the LED Ports can be adjusted to 3 different values: 2, 4 or 10 mA. The LED output is an alternate function of P3.6 an P3.7 and cannot be used while the alternate card function is used. The control register LEDCON is detailed below. Registers Definition Table 40.
Dual Data Pointer T8xC5121 contains a Dual Data Pointer accelerating data memory block moves. The Standard 80C52 Data Pointer is a 16-bit value that is used to address off-chip data RAM or peripherals. In T8xC5121, the standard 16-bit data pointer is called DPTR and located at SFR location 82H and 83H. The second Data Pointer named DPTR1 is located at the same address than the previous one. The DPTR select bit (DPS / bit0) chooses the active pointer and it is located into the AUXR1 register.
A/T8xC5121 Table 43. AUXR1 Register AUXR1 - Dual Pointer Selection Register (A2h) 7 6 5 4 3 2 1 0 - - - - - - - DPS Bit Bit Number Mnemonic 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit.
Memory Management Program Memory All the T8xC5121 versions implement 16 Kbytes of ROM memory, 256 Bytes RAM and 256 Bytes XRAM. The hardware configuration byte and the split of internal memory spaces depends on the product and is detailed below. ROM Configuration Byte Table 44.
A/T8xC5121 Memory Mapping In the products versions, the following internal spaces are defined: • RAM • XRAM • CRAM: 16 KBytes Program RAM Memory • ROM The specific accesses from/to these memories are: • XRAM: if the bit RPS in RCON (described below) is reset, MOVX instructions address the XRAM space. • CRAM: if the bit RPS in RCON is set, MOVX instructions address the CRAM space. Table 46.
If a serial communication device (as described above: TWI or RS232) is detected, the program download its content in the internal EEPROM and in CRAM. Else, the program is internally downloaded from the internal EEPROM into the program CRAM memory (16 Kbytes) Then, in the two cases, the Bootloader executes a Long Jump at address 0000h which initializes the Program counter at the lower address (0000h) of the executable CRAM. Figure 24.
A/T8xC5121 Figure 25. CRAM and ROM Mappings FFFFh F800h entry point C000h Bootloader 3FFFh 16K bytes 256 bytes 0000h ROM CRAM XRAM 256 bytes RAM T83C5121 with Mask ROM Version In this version, the customer program is masked in 16 Kbytes ROM. In-System Programming The In-System Programming (ISP) mode is only implemented in the following product versions: • The customer program is masked in ROM during the final production phase.
Figure 26. Hardware in Relation with the Two Communication Protocols DVCC or Ext. VCC (3V) DVCC Optional Thanks to internal pull-ups TWI P3.2/INT0 P3.7/CRST1 SCL VCC TWI P2.1 P2.0 SDA SDA SCL Internal EEPROM AT24C128 BOOTLOADER VCC VSS EEPROM external AT24C128 Address = 01h (A0 = 1,A1 = 0) DVss Wp = 1 DVCC or Ext.
A/T8xC5121 Bootloader Functional Diagram As described in Section “ROM Configuration Byte”, page 60a ROM bit BLJRB (Boot Loader Jump ROM Bit) defines which product version is. The Bootloader program is mapped in ROM space from address C000h up to FFFFh and the entry point is located at address F800h. Figure 27. Bootloader Flowchart RESET Versions: RAM+ROM RAM,ROM,EEPROM BLJRB = 1 ROM Bit Bootloader Execution versions: RAM+ROM (Pre-prod: Application Program) ROM (Prod) ROM F800h SSB & P3.7 test TWI ext.
In-System Programming Timings The download from the internal EEPROM to CRAM is executed after 4 seconds when operating at 12 MHz frequency. Protection Mechanisms Transfer Checks In order to verify that the transfers are free of errors, a CRC check is implemented during the download of the program in CRAM. This test is done at the end of the 16K space programming.
A/T8xC5121 } void generate_crc_in_frame(void) { checksum_tx=(Uint16) FFFFh; /* init of the crc variable */ /* loop which compute for each byte (data_byte) to load */ checksum_tx=compute_crc((Uint16)data_byte^checksum_tx)^(checksum_tx>>8); /* end of loop */ checksum=~checksum_tx; /* inverts the checksum, so the check will calculate the CRC of all the datas and */ /* will find a constant value = F0B8 which is the CRC_REF const.
The only mean to remove the security level 2 is to send a Full Chip Erase command. Data Bytes SSB Address 3FFD Table 48.
A/T8xC5121 Table 49. Valid Software Security Byte Values SSB Values Functions FE No bypass and level1 security FC No bypass and level2 security BF,BE,BC UART bypass and security levels 7F,7E,7C External TWI bypass and security levels 3F,3E,3C UART and Ext. TWI bypass UART Protocol Overview The serial protocol used is described below.
• Record Type: – • Data/Info: – • Command Description Record Type specifies the command type. This field is used to interpret the remaining information within the frame. The encoding for all the current record types are described in Table 51. Data/Info is a 64 bytes length field. It consists of 64 bytes encoded as pairs of hexadecimal digits. The meaning of data depends on the Record Type.
A/T8xC5121 Autobaud The ISP feature allows a wide range of baud rates in the user application. It is also adaptable to a wide range of oscillator frequencies. This is accomplished by measuring the bit-time of a single bit in a received character. This information is then used to program the baud rate in terms of timer counts based on the oscillator frequency. The ISP feature requires that an initial character (an uppercase U) be sent to the T8xC5121 to establish the baud rate.
Source Target Case Protection UART ISP Intern.
A/T8xC5121 Timers/Counters Introduction The T8xC5121 implements two general-purpose, 16-bit Timer 0s/Counters. Although they are identified as Timer 0, Timer 1, you can independently configure each to operate in a variety of modes as a Timer 0 or as an event Counter. When operating as a Timer 0, a Timer 0/Counter runs for a programmed length of time, then issues an interrupt request. When operating as a Counter, a Timer 0/Counter counts negative transitions on an external pin.
Timer 0 Timer 0 functions as either a Timer 0 or an event Counter in four operating modes. Figure 28 through Figure 31 show the logic configuration of each mode. Timer 0 is controlled by the four lower bits of the TMOD register (see Figure 56) and bits 0, 1, 4 and 5 of the TCON register (see Figure 55). The TMOD register selects the method of Timer 0 gating (GATE0), Timer 0 or Counter operation (T/C0#) and the operating mode (M10 and M00).
A/T8xC5121 Figure 29. Timer 0/Counter x (x = 0 or 1) in Mode 1 FCLK_Periph 0 1 THx (8 bits) TLx (8 bits) Overflow TFx TCON reg Timer 0 x Interrupt Request C/Tx# TMOD reg Tx INTx# GATEx TMOD reg Mode 2 (8-bit Timer 0 with Auto-Reload) TRx TCON reg Mode 2 configures Timer 0 as an 8-bit Timer 0 (TL0 register) that automatically reloads from the TH0 register (see Figure 30). TL0 overflow sets the TF0 flag in the TCON register and reloads TL0 with the contents of TH0, which is preset by the software.
Figure 31. Timer 0/Counter 0 in Mode 3: Two 8-bit Counters FCLK_Periph 0 1 TL0 (8 bits) Overflow TH0 (8 bits) Overflow TF0 TCON.5 Timer 0 Interrupt Request T0 C/T0# TMOD.2 INT0 GATE0 TMOD.3 TR0 TCON.4 FCLK_Periph TF1 TCON.7 Timer 1 Interrupt Request TR1 TCON.
A/T8xC5121 Timer 1 Timer 1 is identical to Timer 0 except for Mode 3 which is a hold-count mode. The following comments help to understand the differences: • Timer 1 functions as either a Timer 0 or an event Counter in the three operating modes. Figure 28 through Figure 30 show the logical configuration for modes 0, 1, and 2. Mode 3 of Timer 1 is a hold-count mode.
Registers Table 55. TCON Register TCON (S:88h) - Timer 0/Counter Control Register 7 6 5 4 3 2 1 0 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Bit Number Bit Mnemonic Description 7 TF1 Timer 1 Overflow flag Cleared by the hardware when processor vectors to interrupt routine. Set by the hardware on Timer 0/Counter overflow when Timer 1 register overflows. 6 TR1 Timer 1 Run Control bit Clear to turn off Timer 0/Counter 1. Set to turn on Timer 0/Counter 1.
A/T8xC5121 Table 56. TMOD Register TMOD (S:89h) - Timer 0/Counter Mode Control Registers 7 6 5 4 3 2 1 0 GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00 Bit Number Bit Mnemonic 7 GATE1 Timer 1 Gating Control bit Clear to enable Timer 1 whenever TR1 bit is set. Set to enable Timer 1 only while INT1 pin is high and TR1 bit is set. 6 C/T1# Timer 1 Counter/Timer 0 Select bit Clear for Timer 0 operation: Timer 1 counts the divided-down system clock.
Table 57. TH0 Register TH0 (S:8Ch) - Timer 0 High Byte Register. 7 Bit Number 6 5 4 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 Bit Mnemonic Description 7:0 High Byte of Timer 0 Reset Value = 0000 0000b Table 58. TL0 Register TL0 (S:8Ah) - Timer 0 Low Byte Register. 7 Bit Number 6 5 4 Bit Mnemonic Description 7:0 Low Byte of Timer 0 Reset Value = 0000 0000b Table 59. TH1 Register TH1 (S:8Dh) - Timer 1 High Byte Register.
A/T8xC5121 Serial I/O Port The serial I/O port is entirely compatible with the serial I/O port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as an Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously and at different baud rates.
Figure 34. UART Timings in Mode 1 RXD D0 D1 D2 D3 D4 D5 D6 D7 Stop Bit Data Byte Start Bit RI SMOD0 = X FE SMOD0 = 1 Figure 35. UART Timings in Modes 2 and 3 RXD D0 Start Bit D1 D2 D3 D4 Data Byte D5 D6 D7 D8 Ninth Bit Stop Bit RI SMOD0 = 0 RI SMOD0 = 1 FE SMOD0 = 1 Automatic Address Recognition The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled (SM2 bit in SCON register is set).
A/T8xC5121 To address a device by its individual address, the SADEN mask byte must be 1111 1111b. For example: SADDR0101 0110b SADEN1111 1100b Given0101 01XXb The following is an example of how to use given addresses to address different slaves: Slave A:SADDR1111 0001b SADEN1111 1010b Given1111 0X0Xb Slave B:SADDR1111 0011b SADEN1111 1001b Given1111 0XX1b Slave C:SADDR1111 0011b SADEN1111 1101b Given1111 00X1b The SADEN byte is selected so that each slave may be addressed separately.
Reset Addresses On reset, the SADDR, SADEN register are initialized to 00h, i.e. the given and broadcast addresses are XXXX XXXXb (all don’t care bits). This ensures that the serial port is backwards compatible with the 80C51 microcontrollers that do not support automatic address recognition. UART Output Configuration Voltage Level The I/O Ports of UART are powered by the EVCC Regulator.
A/T8xC5121 UART Control Registers Table 61. SADEN Register SADEN Slave Address Mask Register (B9h) 7 6 5 4 3 2 1 0 4 3 2 1 0 4 3 2 1 0 Reset Value = 0000 0000b Table 62. SADDR Register SADDR Slave Address Register (A9h) 7 6 5 Reset Value = 0000 0000b Table 63.
UART Timings The following description will be included in L version: Mode Selection SM0 and SM1 bits in SCON register (see Table 67) are used to select a mode among the single synchronous and the three asynchronous modes according to Table 64. Table 64.
A/T8xC5121 Figure 37. Internal Baud Rate Generator Block Diagram PER CLOCK ÷6 0 BRG (8 bits) 1 Overflow ÷2 0 IBRG CLOCK 1 SPD BRR BDRCON.1 BDRCON.4 To Serial Port SMOD1 PCON.7 BRL (8 bits) Synchronous Mode (Mode 0) Mode 0 is a half-duplex, synchronous mode, which is commonly used to expand the I/0 capabilities of a device with shift registers. The transmit data (TXD) pin outputs a set of eight clock pulses while the receive data (RXD) pin transmits or receives a byte of data.
Reception (Mode 0) To start a reception in mode 0, write to SCON register clearing SM0, SM1 and RI bits and setting the REN bit. As shown in Figure 40, Clock is pulsed and the LSB (D0) is sampled on the RXD pin. The D0 bit is then shifted into the shift register. After eight sampling, the MSB (D7) is shifted into the shift register, and hardware asserts RI bit to indicate a completed reception. Software can then read the received byte from SBUF register. Figure 40.
A/T8xC5121 Asynchronous Modes (Modes 1, 2 and 3) The Serial Port has one 8-bit and two 9-bit asynchronous modes of operation. Figure 43 shows the Serial Port block diagram in such asynchronous modes. Figure 43. Serial I/O Port Block Diagram (Modes 1, 2 and 3) SCON.6 SCON.7 SCON.3 SM1 SM0 TB8 Mode Decoder SBUF Tx SR TXD Rx SR RXD M3 M2 M1 M0 T1 CLOCK Mode & Clock Controller IBRG CLOCK SBUF Rx PER CLOCK RB8 SCON.2 SM2 TI RI SCON.4 SCON.1 SCON.
Framing Error Detection (Modes 1, 2 and 3) Framing error detection is provided for the three asynchronous modes. To enable the framing bit error detection feature, set SMOD0 bit in PCON register as shown in Figure 46. When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by two devices. If a valid stop bit is not found, the software sets FE bit in SCON register.
A/T8xC5121 Table 65. Internal Baud Rate Generator Value FPER = 6 MHz1 FPER = 8 MHz1 Baud Rate SPD SMOD1 BRL Error % SPD SMOD1 BRL Error % 115200 - - - - - - - - 57600 - - - - 1 1 247 3.55 38400 1 1 246 2.34 1 1 243 0.16 19200 1 1 236 2.34 1 1 230 0.16 9600 1 1 217 0.16 1 1 204 0.16 4800 1 1 178 0.16 1 1 152 0.16 FPER = 12 MHz2 Baud Rate SPD SMOD1 BRL Error % SPD SMOD1 BRL Error % 115200 - - - - 1 1 247 3.
Table 66. BRL (S:91h) BRL Register Baud Rate Generator Reload Register 7 6 5 4 3 2 1 0 BRL7 BRL6 BRL5 BRL4 BRL3 BRL2 BRL1 BRL0 Bit Number 7-0 Bit Mnemonic Description BRL7:0 Baud Rate Reload Value.
A/T8xC5121 Table 67. SCON Register SCON (S:98h) Serial Control Registe 7 6 5 4 3 2 1 0 FE/SM0 SM1 SM2 REN TB8 RB8 TI RI Bit Number Bit Mnemonic FE Description Framing Error bit To select this function, set SMOD0 bit in PCON register. Set by hardware to indicate an invalid stop bit. Must be cleared by software. 7 SM0 6 SM1 Serial Port Mode bit 0 To select this function, clear SMOD0 bit in PCON register. Software writes to bits SM0 and SM1 to select the Serial Port operating mode.
Table 68. BDRCON Register BDRCON Baud Rate Control Register (9Bh) 7 6 5 4 3 2 1 0 - - - BRR TBCK RBCK SPD SRC Bit Number Bit Mnemonic Description 7 - Reserved The value read from this bit is indeterminate. Do not set this bit 6 - Reserved The value read from this bit is indeterminate. Do not set this bit 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 BRR Baud Rate Run Control bit Clear to stop the Baud Rate. Set to start the Baud Rate.
A/T8xC5121 Table 69. SIOCON Register Serial Input Output Configuration Register Register (91h) 7 6 5 4 3 2 1 0 PMSOEN1 PMSOEN0 - - CPRES RES EVAUTO VEXT0 VEXT1 Bit Number Bit Mnemonic Description Output Enable function on Txd/P3.1 and T0/P3.4: PMSOEN1 PMSOEN0 7-6 PMOSEN1 0 0 PMOS is always off (reset value) PMOSEN0 0 1 PMOS is always driven according to P3.1 or P3.
Hardware Watchdog Timer The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The WDT consists of a 14-bit counter and the Watchdog Timer ReSeT (WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H.
A/T8xC5121 Table 71. WDTPRG Register WDTPRG - Watchdog Timer Out Register (0A7h) 7 6 5 4 3 2 1 0 - - - - - S2 S1 S0 Bit Number Bit Mnemonic Description 7 - 6 - 5 - 4 - 3 - 2 S2 WDT Time-out select bit 2 1 S1 WDT Time-out select bit 1 0 S0 WDT Time-out select bit 0 Reserved The value read from this bit is undetermined. Do not try to set this bit. S2 S1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 S0 0 1 0 1 0 1 0 1 Selected Time-out (214 - 1) machine cycles, 16.
Electrical Characteristics Absolute Maximum Ratings Ambiant Temperature Under Bias ......................-25°C to 85°C Storage Temperature ................................... -65°C to + 150°C Voltage on VCC to VSS ........................................-0.5V to + 6.0V Voltage on Any Pin to VSS .......................... -0.5V to VCC + 0.5V DC Parameters Note: Stresses at or above those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device.
A/T8xC5121 The operating conditions for ICC Tests are the following: Figure 51. ICC Test Condition, Active Mode VCC VCC ICC VCC VCC LI VCC P0 RST EA XTAL2 XTAL1 (NC) CLOCK SIGNAL VSS PLCC52 configuration All other pins are disconnected. Figure 52. ICC Test Condition, Idle Mode VCC VCC ICC VCC P0 RST (NC) CLOCK SIGNAL VCC VCC LI EA XTAL2 XTAL1 VSS PLCC52 configuration All other pins are disconnected. Figure 53.
Table 73. Serial Interface DC parameters (P3.0, P3.1, P3.3 and P3.4) Symbol VIL Parameter Input Low Voltage Min Typ Max Unit Test Conditions -0.5 0.4 V EVCC = 1.8V -0.5 0.5 V EVCC = 2.3V -0.5 0.5 V EVCC = 2.8V External EVcc Automatic EVcc 2.3 1.4 2.8 1.6 VIH Input High Voltage 0.7 x EVCC VOL VOH EICC EVCC 3.3 2.0 EVCC Output Low Voltage Output High Voltage EVCC = 1.8V V EVCC = 2.3V V EVCC = 2.8V V External EVCC Automatic EVcc 0.4 V IOL = 1.2 mA 1.6 1.
A/T8xC5121 Table 75. Smart Card 5V Interface DC Parameters Symbol Parameter Min Max Unit 60 CVCC Card Supply Voltage 4.6 CVCC Ripple on CVcc 105 Test Conditions VCC = 5.4V 121 Card Supply Current CICC Typ mA 102 VCC = 4V VCC = 2.85V 5.4 V 200 mV CIcc = 60 mA 0
Table 78. Smart Card Clock DC Parameters (Port P1.4) Symbol Parameter Min VOL Output Low Voltage IOL Output Low Current VOH Output High Voltage Typ Max Unit 0(1) 0.2 x CV CC V 0(1) 0.4 tR tF 0.7 x CVCC CVCC V IOH = 20 μA (1.8V) 0.7 x CVCC CVCC V IOH = 20 μA (3V) CVCC - 0.5 CVCC V IOH = 50 μA (5V) 15 mA 16 CIN = 30 pF(5V) 22.5 CIN = 30 pF(3V) 50 0.4 x CVCC -0.25 Note: IOL = 50 μA (5V) mA Rise and Fall time Voltage Stability IOL = 20 μΑ (1.
A/T8xC5121 Table 80. Smart Card I/O DC Parameters (P1.0) Symbol Parameter VIL Input Low Voltage IIL Input Low Current VIH Input High Voltage IIH Input High Current Output Low Voltage VOL IOL Output Low Current VOH Output High Voltage IOH tR tF Note: Min Typ Max 0.5 0(1) 0.15 x CVCC 0(1) 0.7 x CVCC Unit V 500 μA CVCC V -20 / +20 μA 0.4 IIH = -20 μA IOL = 1μA (5V) V 0.3 IOL = 1 mA (3V) IOL = 1 mA (1.
Table 82. Smart Card RST, CC4, CC8, DC Parameters (Port P1.5, P1.3, P1.1) Symbol Parameter Output Low Voltage VOL Min Typ 0(1) 0(1) Max Unit 0.12 x CVCC V 0.4 IOL Output Low Current 15 mA VOH Output High Voltage CVCC - 0.5 CVCC V 0.8 x CVCC CVCC (1) IOH Output High Current 15 mA tR tF Rise and Fall delays 0.8 μs Voltage stability Note: IOL = 50 μΑ IOH = 50 μΑ CIN = 30 pF Low level CVCC + 0.25 CVCC -0.5 IOL = 20 μΑ IOH = 20 μΑ 0.4 x CVCC -0.
A/T8xC5121 Typical Application Figure 54. Typical Application Diagram EVCC L1 VCC VCC C1 4.7 µF VSS DVCC C2 4.7 µH LI DVCC or VCC VSS LED0 P3.6 CVSS LED1 Serial Interface OE TxD RxD 100nF VSS CVCC(1)(2)(3) CVCC (4) RTS C3 100nF T0 10µF C4 P3.7 VSS P1.0 CIO P1.1 CC8 P3.4 P1.3 CC4 P1.4 CCLK INT1/OE P3.3 TxD P3.1 RxD P3.0 100nF C5 10 kohm I/O C8 C4 CLK(5) 22 pF 82 pF C6 VSS P1.5 CRST C7 VSS RST Vcc CPRES P1.2 1Mohm (optional resistor) VCC P3.5 VSS CIO1 P3.7 CRST1 CCLK1 P3.
6. Distance between Device pads and Smart Card connector must be less than 4 centimeters. 7. C6,C7 should be as close as possible to the Smart Card connector to reduce noise and interferences.
A/T8xC5121 Ordering Information Code Memory Size (Bytes) Supply Voltage Temperature Range Max Frequency Package Packing Product Marking T83C5121xxxICSIL 16K ROM 2.85 - 5.4V Industrial 16 MHz SSOP24 Stick 83C5121-IL T83C5121xxxICRIL 16K ROM 2.85 - 5.4V Industrial 16 MHz SSOP24 Tape & Reel 83C5121-IL T83C5121xxxS3SIL 16K ROM 2.85 - 5.4V Industrial 16 MHz PLCC52(1) Stick 83C5121-IL T83C5121xxxS3RIL 16K ROM 2.85 - 5.
Package Drawings SSOP24 108 A/T8xC5121 4164G–SCR–07/06
A/T8xC5121 PLCC52 109 4164G–SCR–07/06
QFN32 110 A/T8xC5121 4164G–SCR–07/06
A/T8xC5121 Document Revision History for T8xC5121 Changes from 4164B 06/02 to 4164C - 07/03 1. Ports description update. 2. Added Bootloader Autobaud table. 3. Modified ICC test conditions Figure 51. 4. Added ICCOP power supply current characteristics. 5. Added ICCO pulsed power down mode current characteristics. 6. Modified Smart card characteristics : VCC/CV CC mixed. Changes from 4164C 07/03 to 4164D - 12/03 1. Changed value of EMV to EMV2000. Section “Features”, page 1.
Table of Contents Features ................................................................................................. 1 Description ............................................................................................ 2 Block Diagram ...................................................................................... 2 Pin Description ..................................................................................... 3 Signals ..............................................................
A/T8xC5121 Memory Management ......................................................................... 60 Program Memory ................................................................................................ In-System Programming ..................................................................................... Protection Mechanisms ...................................................................................... Autobaud ....................................................................
Changes from 4164E - 01/04 to 4164F 11/05 .................................................. 111 Changes from 4164F 11/05 to 4164F 07/06..................................................... 111 Table of Contents ..................................................................................
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