Instruction Manual
2
T5760/T5761
4561B–RKE–10/02
Figure 2. Block Diagram
SENS
CDEM
AVCC
AGND
DGND
LNAGND
LNA_IN
DATA
POLLING/_ON
DATA_CLK
DVCC
XTAL
Polling circuit
and
control logic
Rssi Limiter out
Poly-LPF
fg = 7 MHz
LC-VCO
f
:256
XTO
Standby logic
FE CLK
FSK/ASK-
demodulator
and data filter
RSSI IF
Amp.
LNA
4. Order
f0 = 950 kHz/
Dem_out
Sensitivity-
reduction
LPF
fg = 2.2 MHz
IF
Amp.
IC_ACTIVE
Data -
interface
LNAREF
f
:2
Loop-
filter
1 MHz










