Owner manual
Table Of Contents
- Features
- Description
- Pin Configuration
- Pin Description: RF Part
- Pin Description: Microcontroller Part
- UHF ASK/FSK Transmitter Block
- Features
- Description
- General Description
- Functional Description
- Absolute Maximum Ratings
- Thermal Resistance
- Electrical Characteristics
- Microcontroller Block
- Features
- Description
- Introduction
- Microcontroller Architecture General Description
- Components of Microcontroller Core
- Master Reset
- Voltage Monitor
- Clock Generation
- Power-down Modes
- Peripheral Modules
- Bi-directional Ports
- Timer 3
- Features
- Timer/Counter Modes
- Timer 3 – Mode 1: Timer/Counter
- Timer 3 – Mode 2: Timer/Counter, External Trigger Restart and External Capture (with T3I Input)
- Timer 3 – Mode 3: Timer/Counter, Internal Trigger Restart and Internal Capture (with TOG2)
- Timer 3 – Mode 4: Timer/Counter
- Timer 3 – Mode 5: Timer/Counter, External Trigger Restart and External Capture (with T3I Input)
- Timer 3 Modulator/Demodulator Modes
- Timer 3 – Mode 6: Carrier Frequency Burst Modulation Controlled by Timer 2 Output Toggle FlipFlo...
- Timer 3 – Mode 7: Carrier Frequency Burst Modulation Controlled by SSI Internal Output (SO)
- Timer 3 – Mode 8: FSK Modulation with Shift Register Data (SO)
- Timer 3 – Mode 9: Pulse-width Modulation with the Shift Register
- Timer 3 – Mode 10: Manchester Demodulation/Pulse-width Demodulation
- Timer 3 – Mode 11: Biphase Demodulation
- Timer 3 – Mode 12: Timer/Counter with External Capture Mode (T3I)
- Timer 3 Modulator for Carrier Frequency Burst Modulation
- Timer 3 Demodulator for Biphase, Manchester and Pulse-width-modulated Signals
- Timer 3 Registers
- Timer 3 Mode Register (T3M)
- Timer 3 Control Register 1 (T3C) Write
- Timer 3 Status Register 1 (T3ST) Read
- Timer 3 Clock Select Register (T3CS)
- Timer 3 Compare- and Compare-mode Register
- Timer 3 Compare-Mode Register 1 (T3CM1)
- Timer 3 Compare Mode Register 2 (T3CM2)
- Timer 3 COmpare Register 1 (T3CO1) Byte Write
- Timer 3 COmpare Register 2 (T3CO2) Byte Write
- Timer 3 Capture Register
- Synchronous Serial Interface (SSI)
- Serial Interface Registers
- Combination Modes
- Absolute Maximum Ratings
- Thermal Resistance
- DC Operating Characteristics
- AC Characteristics
- Crystal Characteristics
- Ordering Information
- Package Information
- Table of Contents

93
T48C862-R8
4590B–4BMCU–02/03
Write Control Bytes
A -> acknowledge; HB: high byte; LB: low byte; R: row address
Read Operations The EEPROM allows byte-, word- and current address read operations. The read oper-
ations are initiated in the same way as write operations. Every read access is initiated by
sending the START condition followed by the control byte which contains the address
and the read mode. When the device has received a read command, it returns an
acknowledge, loads the addressed word into the read/write buffer and sends the
selected data byte to the master. The master has to acknowledge the received byte if it
wants to proceed the read operation. If two bytes are read out from the buffer the device
increments respectively decrements the word address automatically and loads the
buffer with the next word. The read mode bits determines if the low or high byte is read
first from the buffer and if the word address is incremented or decremented for the next
read access. If the memory address limit is reached, the data word address will roll over
and the sequential read will continue. The master can terminate the read operation after
every byte by not responding with an acknowledge (N) and by issuing a stop condition.
Read One Data Byte
Read Two Data Bytes
Read n Data Bytes
Read Control Bytes
MSB LSB
Write low byte first A4 A3 A2 A1 A0 C1 C0 R/NW
Row address 0 1 0
Byte order LB(R) HB(R)
MSB LSB
Write high byte first A4 A3 A2 A1 A0 C1 C0 R/NW
Row address 1 0 0
Byte order HB(R) LB(R)
Start Control byte A Data byte 1 N Stop
Start Control byte A Data byte 1 A Data byte 2 N Stop
Start Control byte A Data byte 1 A Data byte 2 A - - - Data byte n N Stop
MSB LSB
Read low byte first,
address increment
A4 A3 A2 A1 A0 C1 C0 R/NW
Row address 0 1 1
Byte order LB(R) HB(R) LB(R+1) HB(R+1) - - - LB(R+n) HB(R+n)
MSB LSB










