Owner manual

83
T48C862-R8
4590B–4BMCU–02/03
Figure 79. FSK Modulation
Combination Mode 7:
Pulse-width Modulation
(PWM)
SSI mode 1: 8-bit shift register internal data output (SO) to the Timer 3
Timer 3 mode 9: Pulse-width modulation with the shift register data (SO)
The two compare registers are used to generate two varied time intervals. The SSI data
output selects which compare register is used for the output pulse generation. In this
mode, both compare and compare mode registers must be programmed to generate the
two pulse width. It is also useful to enable the single-action mode for extreme duty
cycles. Timer 2 is used as baudrate generator and for the triggered restart of Timer 3.
The SSI must be supplied with the toggle signal of Timer 2. The counter is driven by an
internal or external clock source.
Figure 80. Pulse-width Modulation
Combination Mode 8:
Manchester
Demodulation/Pulse-width
Demodulation
SSI mode 1: 8-bit shift register internal data input (SI) and the internal shift clock
(SCI) from the Timer 3
Timer 3 mode 10: Manchester demodulation/pulse-width demodulation with Timer 3
For Manchester demodulation, the edge detection stage must be programmed to detect
each edge at the input. These edges are evaluated by the demodulator stage. The timer
stage is used to generate the shift clock for the SSI. A compare register 1 match event
defines the correct moment for shifting the state from the input T3I as the decoded bit
into shift register. After that, the demodulator waits for the next edge to synchronize the
timer by a reset for the next bit. The compare register 2 can be used to detect a time
error and handle it with an interrupt routine.
01234012340120
Counter 3
CM31
CM32
SO
12012012012012012012012340
T3R
12
T3O
3
01 0
40
000000000 0000
Counter 3
CM31
CM32
T3O
00000123456789101112131415012345
TOG2
678
1
9111210 1413 0 2 314150
00 1
SIR
SO
SCO
T3R