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Table Of Contents

Features
Description
Pin Configuration
Pin Description: RF Part
Pin Description: Microcontroller Part
UHF ASK/FSK Transmitter Block
Features
Description
General Description
Functional Description
- ASK Transmission
- FSK Transmission
- CLK Output
  - Clock Pulse Take Over
  - Output Matching and Power Setting
- Application Circuit
Absolute Maximum Ratings
Thermal Resistance
Electrical Characteristics
Microcontroller Block
Features
Description
Introduction
- Differences between T48C862-R8 and ATAR862 Microconrtollers
Microcontroller Architecture General Description
Components of Microcontroller Core
- Program Memory
- RAM
  - Expression Stack
  - Return Stack
- Registers
- ALU
- I/O Bus
- Instruction Set
- Interrupt Structure
  - Interrupt Processing
  - Interrupt Latency
- Software Interrupts
- Hardware Interrupts
Master Reset
- Power-on Reset and Brown-out Detection
  - Watchdog Reset
  - External Clock Supervisor
Voltage Monitor
- Voltage Monitor Control/Status Register
Clock Generation
- Clock Module
- Oscillator Circuits and External Clock Input Stage
- Clock Management
  - Clock Management Register (CM)
  - System Configuration Register (SC)
Power-down Modes
Peripheral Modules
- Addressing Peripherals
Bi-directional Ports
- Bi-directional Port 1
- Bi-directional Port 2
  - Port 2 Data Register (P2DAT)
  - Port 2 Control Register (P2CR)
- Bi-directional Port 5
  - Port 5 Data Register (P5DAT)
  - Port 5 Control Register (P5CR) Byte Write
- Bi-directional Port 4
  - Port 4 Data Register (P4DAT)
  - Port 4 Control Register (P4CR) Byte Write
- Bi-directional Port 6
  - Port 6 Data Register (P6DAT)
  - Port 6 Control Register (P6CR)
- Universal Timer/Counter/ Communication Module (UTCM)
- Timer 1
- Timer 2
- Timer 2 Modes
- Timer 2 Output Modes
- Timer 2 Output Signals
- Timer 2 Registers
Timer 3
- Features
- Timer/Counter Modes
- Timer 3 Modulator/Demodulator Modes
- Timer 3 Modulator for Carrier Frequency Burst Modulation
- Timer 3 Demodulator for Biphase, Manchester and Pulse-width-modulated Signals
- Timer 3 Registers
- Timer 3 Capture Register
  - Timer 3 CaPture Register (T3CP) Byte Read
- Synchronous Serial Interface (SSI)
- Serial Interface Registers
Combination Modes
- Combination Mode Timer 2 and SSI
- Combination Mode Timer 3 and SSI
- Combination Mode Timer 2 and Timer 3
  - Combination Mode 10: Frequency Measurement or Event Counter with Time Gate
  - Combination Mode 11: Burst Modulation 1
- Combination Mode Timer 2, Timer 3 and SSI
  - Combination Mode 12: Burst Modulation 2
  - Combination Mode 13: FSK Modulation
- Data EEPROM
- Serial Interface
  - Serial Protocol
  - Control Byte Format
- EEPROM
- Initialization the Serial Interface to the EEPROM
Absolute Maximum Ratings
Thermal Resistance
DC Operating Characteristics
AC Characteristics
Crystal Characteristics
Ordering Information
Package Information
Table of Contents

T48C862-R8

4590B–4BMCU–02/03

Figure 70. MCL Bus Protocol 2

SSI Interrupt The SSI interrupt INT3 can be generated either by an SSI buffer register status (i.e.,

transmit buffer empty or receive buffer full), the end of SSI data telegram or on the fall-

ing edge of the SC/SD pins on Port 4 (see P4CR). SSI interrupt selection is performed

by the Interrupt FunctioN control bit (IFN). The SSI interrupt is usually used to synchro-

nize the software control of the SSI and inform the controller of the present SSI status.

The Port 4 interrupts can be used together with the SSI or, if the SSI itself is not

required, as additional external interrupt sources. In either case this interrupt is capable

of waking the controller out of sleep mode.

To enable and select the SSI relevant interrupts use the SSI interrupt mask (SIM) and

the Interrupt Function (IFN) while the Port 4 interrupts are enabled by setting appropri-

ate control bits in P4CR register.

Modulation and Demodulation If the shift register is used together with Timer 2 or Timer 3 for modulation or demodula-

tion purposes, the 8-bit synchronous mode must be used. In this case, the unused Port

4 pins can be used as conventional bi-directional ports.

The modulation and demodulation stages, if enabled, operate as soon as the SSI is acti-

vated (SIR = 0) and cease when deactivated (SIR = 1).

Due to the byte-orientated data control, the SSI (when running normally) generates

serial bit streams which are submultiples of 8 bits. An SSI output masking (OMSK) func-

tion permits; however, the generation of bit streams of any length. The OMSK signal is

derived indirectly from the 4-bit prescaler of the Timer 2 and masks out a programmable

number of unrequired trailing data bits during the shifting out of the final data word in the

bit stream. The number of non-masked data bits is defined by the value pre-pro-

grammed in the prescaler compare register. To use output masking, the modulator stop

mode bit (MSM) must be set to "0" before programming the final data word into the SSI

transmit buffer. This in turn, enables shift clocks to the prescaler when this final word is

shifted out. On reaching the compare value, the prescaler triggers the OMSK signal and

all following data bits are blanked.

Start

1n89

1st Bit 8th Bit ACK Stop