Owner manual

65
T48C862-R8
4590B–4BMCU–02/03
Timer 3 Compare Mode
Register 2 (T3CM2)
Address: "B"hex - Subaddress: "3"hex
T3CM2 contains the mask bits for the match event of Counter 3 compare register 2
The compare registers and corresponding counter reset masks can be used to program
the counter time intervals and the toggle masks can be used to program output signal.
The single-action mask can also be used in this mode. It starts operating after the timer
started with T3R.
Timer 3 COmpare Register 1
(T3CO1) Byte Write
Address: "B"hex - Subaddress: "4"hex
Timer 3 COmpare Register 2
(T3CO2) Byte Write
Address: "B"hex - Subaddress: "5"hex
Bit 3Bit 2Bit 1Bit 0
T3CM2 T3SM2 T3TM2 T3RM2 T3IM2 Reset value: 0000b
T3SM2 Timer 3 Single action Mask bit 2
T3SM2 = 0, disables single-action compare mode
T3SM2 = 1, enables single-compare mode. After this bit is set, the compare
register (T3CO2) is used until the next compare match.
T3TM2 Timer 3 compare Toggle action Mask bit 2
T3TM2 = 0, disables compare toggle
T3TM2 = 1, enables compare toggle. A match of Counter 3 with the compare
register (T3CO2) toggles the output flip-flop (TOG3).
T3RM2 Timer 3 Reset Mask bit 2
T3RM2 = 0, disables counter reset
T3RM2 = 1, enables counter reset. A match of Counter 3 with the compare
register (T3CO2) resets the Counter 3.
T3IM2 Timer 3 Interrupt Mask bit 2
T3RM2 = 0, disables Timer 3 interrupt for T3CO2 register.
T3RM2 = 1, enables Timer 3 interrupt for T3CO2 register.
High Nibble
Second write cycle Bit 7 Bit 6 Bit 5 Bit 4 Reset value: 1111b
Low Nibble
First write cycle Bit 3 Bit 2 Bit15 Bit 0 Reset value: 1111b
High Nibble
Second write cycle Bit 7 Bit 6 Bit 5 Bit 4 Reset value: 1111b
Low Nibble
First write cycle Bit 3 Bit 2 Bit15 Bit 0 Reset value: 1111b