Owner manual
Table Of Contents
- Features
- Description
- Pin Configuration
- Pin Description: RF Part
- Pin Description: Microcontroller Part
- UHF ASK/FSK Transmitter Block
- Features
- Description
- General Description
- Functional Description
- Absolute Maximum Ratings
- Thermal Resistance
- Electrical Characteristics
- Microcontroller Block
- Features
- Description
- Introduction
- Microcontroller Architecture General Description
- Components of Microcontroller Core
- Master Reset
- Voltage Monitor
- Clock Generation
- Power-down Modes
- Peripheral Modules
- Bi-directional Ports
- Timer 3
- Features
- Timer/Counter Modes
- Timer 3 – Mode 1: Timer/Counter
- Timer 3 – Mode 2: Timer/Counter, External Trigger Restart and External Capture (with T3I Input)
- Timer 3 – Mode 3: Timer/Counter, Internal Trigger Restart and Internal Capture (with TOG2)
- Timer 3 – Mode 4: Timer/Counter
- Timer 3 – Mode 5: Timer/Counter, External Trigger Restart and External Capture (with T3I Input)
- Timer 3 Modulator/Demodulator Modes
- Timer 3 – Mode 6: Carrier Frequency Burst Modulation Controlled by Timer 2 Output Toggle FlipFlo...
- Timer 3 – Mode 7: Carrier Frequency Burst Modulation Controlled by SSI Internal Output (SO)
- Timer 3 – Mode 8: FSK Modulation with Shift Register Data (SO)
- Timer 3 – Mode 9: Pulse-width Modulation with the Shift Register
- Timer 3 – Mode 10: Manchester Demodulation/Pulse-width Demodulation
- Timer 3 – Mode 11: Biphase Demodulation
- Timer 3 – Mode 12: Timer/Counter with External Capture Mode (T3I)
- Timer 3 Modulator for Carrier Frequency Burst Modulation
- Timer 3 Demodulator for Biphase, Manchester and Pulse-width-modulated Signals
- Timer 3 Registers
- Timer 3 Mode Register (T3M)
- Timer 3 Control Register 1 (T3C) Write
- Timer 3 Status Register 1 (T3ST) Read
- Timer 3 Clock Select Register (T3CS)
- Timer 3 Compare- and Compare-mode Register
- Timer 3 Compare-Mode Register 1 (T3CM1)
- Timer 3 Compare Mode Register 2 (T3CM2)
- Timer 3 COmpare Register 1 (T3CO1) Byte Write
- Timer 3 COmpare Register 2 (T3CO2) Byte Write
- Timer 3 Capture Register
- Synchronous Serial Interface (SSI)
- Serial Interface Registers
- Combination Modes
- Absolute Maximum Ratings
- Thermal Resistance
- DC Operating Characteristics
- AC Characteristics
- Crystal Characteristics
- Ordering Information
- Package Information
- Table of Contents

63
T48C862-R8
4590B–4BMCU–02/03
Timer 3 Control Register 1
(T3C) Write
Primary register address: "C"hex - Write
Timer 3 Status Register 1
(T3ST) Read
Primary register address: "C"hex - Read
Note: The status bits T3C1, T3C2 and T3ED will be reset after a READ access to T3ST.
Timer 3 Clock Select Register
(T3CS)
Address: "B"hex - Subaddress: "1"hex
Bit 3Bit 2Bit 1Bit 0
Write T3EIM T3TOP T3TS T3R Reset value: 0000b
T3EIM Timer 3 Edge Interrupt Mask
T3EIM = 0, disables the interrupt when an edge event for Timer 3 occurs (T3I)
T3EIM = 1, enables the interrupt when an edge event for Timer 3 occurs (T3I)
T3TOP Timer 3 Toggle Output Preset T3TOP = 0, sets toggle output (M3) to "0"
T3TOP = 1, sets toggle output (M3) to "1"
Note: If T3R = 1, no output preset is possible
T3TS Timer 3 Toggle with Start T3TS = 0, Timer 3 output is not toggled during the start
T3TS = 1, Timer 3 output is toggled if started with T3R
T3R Timer 3 Run T3R = 0, Timer 3 stop and reset
T3R = 1, Timer 3 run
Bit 3Bit 2Bit 1Bit 0
Read - - - T3ED T3C2 T3C1 Reset value: x000b
T3ED Timer 3 Edge Detect
This bit will be set by the edge-detect logic of Timer 3 input (T3I)
T3C2 Timer 3 Compare 2
This bit will be set when a match occurs between Counter 3 and T3CO2
T3C1 Timer 3 Compare 1
This bit will be set when a match occurs between Counter 3 and T3CO1
Bit 3 Bit 2 Bit 1 Bit 0
T3CS T3E1 T3E0 T3CS1 T3CS0 Reset value: 1111b
T3E1 Timer 3 Edge select bit 1 T3E1 T3E0 Timer 3 Input Edge Select (T3I)
T3E0 Timer 3 Edge select bit 0 1 1 - - -
1 0 Positive edge at T3I pin
0 1 Negative edge at T3I pin
0 0 Each edge at T3I pin










