Owner manual

56
T48C862-R8
4590B–4BMCU–02/03
Figure 50. Counter 3 Stage
The status of the timer as well as the occurrence of a compare match or an edge detect
of the input signal is indicated by the status register T2ST. This allows identification of
the interrupt source because all these events share only one timer interrupt.
Timer 3 compares data values.
The Timer 3 has two 8-bit compare registers (T3CO1, T3CO2). The compare data value
can be ‘m’ for each of the Timer 3 compare registers.
The compare data value for the compare registers is: m = x +1 0 £ x £ 255
Timer 3 – Mode 1:
Timer/Counter
The selected clock from an internal or external source increments the 8-bit counter. In
this mode, the timer can be used as event counter for external clocks at T3I or as timer
for generating interrupts and pulses at T3O. The counter value can be read by the soft-
ware via the capture register.
8-bit comparator
Compare register 1
RES
Capture register
8-bit counter
Compare register 2
Control
C31
C32
Control
T3SM1
NQ
D
T3RM1 T3IM1 T3TM1
TOG2 T3I
T3TM2T3IM2T3RM2T3SM2
NQ
D
CL3
T3EIM
TOG3
INT5
CM31
CM32
: T3M1
: T3M2