Owner manual

51
T48C862-R8
4590B–4BMCU–02/03
Timer 2 Mode Register 1
(T2M1)
Address: "7"hex - Subaddress: "1"hex
Duty Cycle Generator The duty cycle generator generates duty cycles of 25%, 33% or 50%. The frequency at
the duty cycle generator output depends on the duty cycle and the Timer 2 prescaler
setting. The DCG-stage can also be used as additional programmable prescaler for
Timer 2.
Bit 3Bit 2Bit 1Bit 0
T2D1 T2D0 T2MS1 T2MS0 Reset value: 1111b
T2D1 Timer 2 Duty cycle bit 1
T2D0 Timer 2 Duty cycle bit 0
T2D1 T2D0 Function of Duty Cycle Generator (DCG) Additional Divider Effect
1 1 Bypassed (DCGO0) /1
1 0 Duty cycle 1/1 (DCGO1) /2
0 1 Duty cycle 1/2 (DCGO2) /3
0 0 Duty cycle 1/3 (DCGO3) /4
T2MS1 Timer 2 Mode Select bit 1
T2MS0 Timer 2 Mode Select bit 0
Mode T2MS1 T2MS0 Clock Output (POUT) Timer 2 Modes
1 1 1 4-bit counter overflow (OVF1) 12-bit compare counter; the
DCG has to be bypassed in
this mode
2 1 0 4-bit compare output (CM1) 8-bit compare counter with
4-bit programmable prescaler
and duty cycle generator
3 0 1 4-bit compare output (CM1) 8-bit compare counter clocked
by SYSCL or the external clock
input T2I, 4-bit prescaler run,
the counter 2/1 starts after
writing mode 3
4 0 0 4-bit compare output (CM1) 8-bit compare counter clocked
by SYSCL or the external clock
input T2I, 4-bit prescaler stop
and resets