Owner manual
Table Of Contents
- Features
- Description
- Pin Configuration
- Pin Description: RF Part
- Pin Description: Microcontroller Part
- UHF ASK/FSK Transmitter Block
- Features
- Description
- General Description
- Functional Description
- Absolute Maximum Ratings
- Thermal Resistance
- Electrical Characteristics
- Microcontroller Block
- Features
- Description
- Introduction
- Microcontroller Architecture General Description
- Components of Microcontroller Core
- Master Reset
- Voltage Monitor
- Clock Generation
- Power-down Modes
- Peripheral Modules
- Bi-directional Ports
- Timer 3
- Features
- Timer/Counter Modes
- Timer 3 – Mode 1: Timer/Counter
- Timer 3 – Mode 2: Timer/Counter, External Trigger Restart and External Capture (with T3I Input)
- Timer 3 – Mode 3: Timer/Counter, Internal Trigger Restart and Internal Capture (with TOG2)
- Timer 3 – Mode 4: Timer/Counter
- Timer 3 – Mode 5: Timer/Counter, External Trigger Restart and External Capture (with T3I Input)
- Timer 3 Modulator/Demodulator Modes
- Timer 3 – Mode 6: Carrier Frequency Burst Modulation Controlled by Timer 2 Output Toggle FlipFlo...
- Timer 3 – Mode 7: Carrier Frequency Burst Modulation Controlled by SSI Internal Output (SO)
- Timer 3 – Mode 8: FSK Modulation with Shift Register Data (SO)
- Timer 3 – Mode 9: Pulse-width Modulation with the Shift Register
- Timer 3 – Mode 10: Manchester Demodulation/Pulse-width Demodulation
- Timer 3 – Mode 11: Biphase Demodulation
- Timer 3 – Mode 12: Timer/Counter with External Capture Mode (T3I)
- Timer 3 Modulator for Carrier Frequency Burst Modulation
- Timer 3 Demodulator for Biphase, Manchester and Pulse-width-modulated Signals
- Timer 3 Registers
- Timer 3 Mode Register (T3M)
- Timer 3 Control Register 1 (T3C) Write
- Timer 3 Status Register 1 (T3ST) Read
- Timer 3 Clock Select Register (T3CS)
- Timer 3 Compare- and Compare-mode Register
- Timer 3 Compare-Mode Register 1 (T3CM1)
- Timer 3 Compare Mode Register 2 (T3CM2)
- Timer 3 COmpare Register 1 (T3CO1) Byte Write
- Timer 3 COmpare Register 2 (T3CO2) Byte Write
- Timer 3 Capture Register
- Synchronous Serial Interface (SSI)
- Serial Interface Registers
- Combination Modes
- Absolute Maximum Ratings
- Thermal Resistance
- DC Operating Characteristics
- AC Characteristics
- Crystal Characteristics
- Ordering Information
- Package Information
- Table of Contents
41
T48C862-R8
4590B–4BMCU–02/03
Timer 1 can also be used as a watchdog timer to prevent a system from stalling. The
watchdog timer is a 3-bit counter that is supplied by a separate output of Timer 1. It gen-
erates a system reset when the 3-bit counter overflows. To avoid this, the 3-bit counter
must be reset before it overflows. The application software has to accomplish this by
reading the CWD register.
After power-on reset the watchdog must be activated by software in the $RESET initial-
ization routine. There are two watchdog modes, in one mode the watchdog can be
switched on and off by software, in the other mode the watchdog is active and locked.
This mode can only be stopped by carrying out a system reset.
The watchdog timer operation mode and the time interval for the watchdog reset can be
programmed via the watchdog control register (WDC).
Figure 33. Timer 1 Module
Figure 34. Timer 1 and Watchdog
Prescaler
14 bit
CL1
Watchdog
4 bit
MUX
WDCL
T1IM
T1BP
T1MUX
NRST
INT2
T1OUT
T1CS
SYSCL
SUBCL
Q5Q1 Q2 Q3 Q4
Q6
Q8
Q8
Q11
Q11
Q14
Q14
RES
CL
Decoder
Watchdog
mode control
MUX for interval timer
Decoder
MUX for watchdog timer
T1RM T1C2 T1C1 T1C0
3
2
WDL WDR WDT1 WDT0
WDC
RES
T1MUX
SUBCL
T1BP T1IM
T1IM=0
T1IM=1
INT2
T1OUT
T1C2
RESET
(NRST)
Watchdog
Divider / 8
Divider
RESET
T1C1
Write of the
T1C1 register
CL1
WDCL
Read of the
CWD register