Owner manual
Table Of Contents
- Features
- Description
- Pin Configuration
- Pin Description: RF Part
- Pin Description: Microcontroller Part
- UHF ASK/FSK Transmitter Block
- Features
- Description
- General Description
- Functional Description
- Absolute Maximum Ratings
- Thermal Resistance
- Electrical Characteristics
- Microcontroller Block
- Features
- Description
- Introduction
- Microcontroller Architecture General Description
- Components of Microcontroller Core
- Master Reset
- Voltage Monitor
- Clock Generation
- Power-down Modes
- Peripheral Modules
- Bi-directional Ports
- Timer 3
- Features
- Timer/Counter Modes
- Timer 3 – Mode 1: Timer/Counter
- Timer 3 – Mode 2: Timer/Counter, External Trigger Restart and External Capture (with T3I Input)
- Timer 3 – Mode 3: Timer/Counter, Internal Trigger Restart and Internal Capture (with TOG2)
- Timer 3 – Mode 4: Timer/Counter
- Timer 3 – Mode 5: Timer/Counter, External Trigger Restart and External Capture (with T3I Input)
- Timer 3 Modulator/Demodulator Modes
- Timer 3 – Mode 6: Carrier Frequency Burst Modulation Controlled by Timer 2 Output Toggle FlipFlo...
- Timer 3 – Mode 7: Carrier Frequency Burst Modulation Controlled by SSI Internal Output (SO)
- Timer 3 – Mode 8: FSK Modulation with Shift Register Data (SO)
- Timer 3 – Mode 9: Pulse-width Modulation with the Shift Register
- Timer 3 – Mode 10: Manchester Demodulation/Pulse-width Demodulation
- Timer 3 – Mode 11: Biphase Demodulation
- Timer 3 – Mode 12: Timer/Counter with External Capture Mode (T3I)
- Timer 3 Modulator for Carrier Frequency Burst Modulation
- Timer 3 Demodulator for Biphase, Manchester and Pulse-width-modulated Signals
- Timer 3 Registers
- Timer 3 Mode Register (T3M)
- Timer 3 Control Register 1 (T3C) Write
- Timer 3 Status Register 1 (T3ST) Read
- Timer 3 Clock Select Register (T3CS)
- Timer 3 Compare- and Compare-mode Register
- Timer 3 Compare-Mode Register 1 (T3CM1)
- Timer 3 Compare Mode Register 2 (T3CM2)
- Timer 3 COmpare Register 1 (T3CO1) Byte Write
- Timer 3 COmpare Register 2 (T3CO2) Byte Write
- Timer 3 Capture Register
- Synchronous Serial Interface (SSI)
- Serial Interface Registers
- Combination Modes
- Absolute Maximum Ratings
- Thermal Resistance
- DC Operating Characteristics
- AC Characteristics
- Crystal Characteristics
- Ordering Information
- Package Information
- Table of Contents

37
T48C862-R8
4590B–4BMCU–02/03
Table 6. P5xM2, P5xM1 – Port 5x Interrupt Mode/Direction Code
Bi-directional Port 4 The bi-directional Port 4 is a bitwise configurable I/O port and provides the external pins
for the Timer 2, SSI and the voltage monitor input (VMI). As a normal port, it performs in
exactly the same way as bi-directional Port 2 (see Figure 31). Two additional multi-
plexes allow data and port direction control to be passed over to other internal modules
(Timer 2, VM or SSI). The I/O-pins for SC and SD line have an additional mode to
generate an SSI-interrupt.
All four Port 4 pins can be individually switched by the P4CR-register. Figure 31 shows
the internal interfaces to bi-directional Port 4.
Figure 31. Bi-directional Port 4 and Port 6
Auxiliary Address: "5"hex, First Write Cycle Second Write Cycle
Code
3 2 1 0 Function
Code
3 2 1 0 Function
x x 1 1 BP50 in input mode
– interrupt disabled x x 1 1 BP52 in input mode – interrupt disabled
x x 0 1 BP50 in input mode
– rising edge interrupt x x 0 1 BP52 in input mode – rising edge interrupt
x x 1 0 BP50 in input mode
– falling edge interrupt x x 1 0 BP52 in input mode – falling edge interrupt
x x 0 0 BP50 in output mode
– interrupt disabled x x 0 0 BP52 in output mode – interrupt disabled
1 1 x x BP51 in input mode
– interrupt disabled 1 1 x x BP53 in input mode – interrupt disabled
0 1 x x BP51 in input mode
– rising edge interrupt 0 1 x x BP53 in input mode – rising edge interrupt
1 0 x x BP51 in input mode
– falling edge interrupt 1 0 x x BP53 in input mode – falling edge interrupt
0 0 x x BP51 in output mode
– interrupt disabled 0 0 x x BP53 in output mode – interrupt disabled
Master reset
Q
V
DD
V
DD
BPxy
Configurable
*
*
PxDATy
I/O Bus
D
I/O Bus
I/O Bus
*
*
Switched
pull-up
Switched
pull-down
*
*
S
PxCRy
S
QD
PxMRy
POut
(Direction)
PDir
Intx
*
*
PIn
V
DD
Static
pull-up
Static
pull-down










