Owner manual
Table Of Contents
- Features
- Description
- Pin Configuration
- Pin Description: RF Part
- Pin Description: Microcontroller Part
- UHF ASK/FSK Transmitter Block
- Features
- Description
- General Description
- Functional Description
- Absolute Maximum Ratings
- Thermal Resistance
- Electrical Characteristics
- Microcontroller Block
- Features
- Description
- Introduction
- Microcontroller Architecture General Description
- Components of Microcontroller Core
- Master Reset
- Voltage Monitor
- Clock Generation
- Power-down Modes
- Peripheral Modules
- Bi-directional Ports
- Timer 3
- Features
- Timer/Counter Modes
- Timer 3 – Mode 1: Timer/Counter
- Timer 3 – Mode 2: Timer/Counter, External Trigger Restart and External Capture (with T3I Input)
- Timer 3 – Mode 3: Timer/Counter, Internal Trigger Restart and Internal Capture (with TOG2)
- Timer 3 – Mode 4: Timer/Counter
- Timer 3 – Mode 5: Timer/Counter, External Trigger Restart and External Capture (with T3I Input)
- Timer 3 Modulator/Demodulator Modes
- Timer 3 – Mode 6: Carrier Frequency Burst Modulation Controlled by Timer 2 Output Toggle FlipFlo...
- Timer 3 – Mode 7: Carrier Frequency Burst Modulation Controlled by SSI Internal Output (SO)
- Timer 3 – Mode 8: FSK Modulation with Shift Register Data (SO)
- Timer 3 – Mode 9: Pulse-width Modulation with the Shift Register
- Timer 3 – Mode 10: Manchester Demodulation/Pulse-width Demodulation
- Timer 3 – Mode 11: Biphase Demodulation
- Timer 3 – Mode 12: Timer/Counter with External Capture Mode (T3I)
- Timer 3 Modulator for Carrier Frequency Burst Modulation
- Timer 3 Demodulator for Biphase, Manchester and Pulse-width-modulated Signals
- Timer 3 Registers
- Timer 3 Mode Register (T3M)
- Timer 3 Control Register 1 (T3C) Write
- Timer 3 Status Register 1 (T3ST) Read
- Timer 3 Clock Select Register (T3CS)
- Timer 3 Compare- and Compare-mode Register
- Timer 3 Compare-Mode Register 1 (T3CM1)
- Timer 3 Compare Mode Register 2 (T3CM2)
- Timer 3 COmpare Register 1 (T3CO1) Byte Write
- Timer 3 COmpare Register 2 (T3CO2) Byte Write
- Timer 3 Capture Register
- Synchronous Serial Interface (SSI)
- Serial Interface Registers
- Combination Modes
- Absolute Maximum Ratings
- Thermal Resistance
- DC Operating Characteristics
- AC Characteristics
- Crystal Characteristics
- Ordering Information
- Package Information
- Table of Contents

34
T48C862-R8
4590B–4BMCU–02/03
Figure 27. Bi-directional Port 1
Bi-directional Port 2 As all other bi-directional ports, this port includes a bitwise programmable Control Reg-
ister (P2CR), which enables the individual programming of each port bit as input or
output. It also opens up the possibility of reading the pin condition when in output mode.
This is a useful feature for self testing and for serial bus applications.
Port 2, however, has an increased drive capability and an additional low resistance
pull-up/pull-down transistor mask option.
Care should be taken connecting external components to BP20/NTE. During any reset
phase, the BP20/NTE input is driven towards V
DD
by an additional internal strong pull-up
transistor. This pin must not be pulled down (active or passive) to V
SS
during reset by
any external circuitry representing a resistor of less than 150 kW. This prevents the cir-
cuit from unintended switching to test mode enable through the application circuitry at
pin BP20/NTE. Resistors less than 150 kW might lead to an undefined state of the inter-
nal test logic thus disabling the application firmware.
To avoid any conflict with the optional internal pull-down transistors, BP20 handles the
pull-down options in a different way than all other ports. BP20 is the only port that
switches off the pull-down transistors during reset.
Figure 28. Bi-directional Port 2
OUT
IN
Reset
I/O Bus
D
R
S
Q
Q
NQ
R
Master reset
P1DATy
(Data out)
(Direction)
BP1y
V
DD
*
Switched
pull-up
*
**
*
*) Configurable
V
DD
Static
pull-up
Static
pull-down
Switched
pull-down
Master reset
Q
Q
BP2y
Configurable
*
*
P2DATy
P2CRy
I/O Bus
D
I/O Bus
I/O Bus
*
*
Switched
pull-up
*
Static
Pull-up
(Data out)
(Direction)
*
S
D
*
S
*
V
DD
Static
Pull-down
Switched
pull-down
V
DD










