Owner manual

31
T48C862-R8
4590B–4BMCU–02/03
Figure 26. Example of I/O Addressing
1
2
3
4
5
Module ASW
Module M1
Module M2 Module M3
Auxiliary Switch
Module
Primary Reg.
(Address Pointer)
Subaddress Reg.
Bank of
Primary Reg.
to other modules
Subport Fh
Subport Eh
Subport 1
Subport 0
Primary Reg.
Aux. Reg.
Primary Reg.
I/O bus
Example of
qFORTH
program code
Indirect Subport Access
(Subport Register Write)
1 Addr. (SPort) Addr. (M1) OUT
2 SPort _Data Addr. (M1) OUT
(Subport Register Read)
1 Addr. (SPort) Addr. (M1) OUT
2 Addr. (M1) IN
(Subport Register Write Byte)
1 Addr. (SPort) Addr. (M1) OUT
(Subport Register Read Byte)
1 Addr. (SPort) Addr. (M1) OUT
2 Addr. (M1) IN (hi)
2 Addr. (M1) IN (lo)
3 Prim._Data Addr. (M2) OUT
4 Addr. (M2) Addr. (ASW) OUT
4 Addr. (M2) Addr. (ASW) OUT
Dual Register Access
(Primary Register Write)
(Auxiliary Register Write)
5 Aux._Data Addr. (M2) OUT
(Primary Register Read)
5 Addr. (M2) IN
(Auxiliary Register Read)
3 Addr. (M2) IN
(Auxiliary Register Write Byte)
4 Addr. (M2) Addr. (ASW) OUT
5 Aux._Data (lo) Addr. (M2) OUT
5 Aux._Data (hi) Addr. (M2) OUT
6 Prim._Data Addr.(M3) OUT
Single Register Access
(Primary Register Write)
6 Addr. (M3) IN
(Primary Register Read)
2 SPort _Data(lo) Addr. (M1) OUT
2 SPort _Data(hi) Addr. (M1) OUT
6
Addr.(ASW) = Auxiliary Switch Module address
Addr.(Mx) = Module Mx address
Addr.(SPort) = Subport address
Prim._Data = Data to be written into Primary Register
Aux._Data = Data to be written into Auxiliary Register
Prim._Data(lo)= Data to be written into Auxiliary Register (low nibble)
Prim._Data(hi) = Data to be written into Auxiliary Register (high nibble)
SPort_Data(lo) = Data to be written into SubPort (low nibble)
SPort_Data(hi) = Data to be written into SubPort (high nibble)
(lo) = SPort_Data (low nibble)
(hi) = SPort_Data (high nibble)