Owner manual
Table Of Contents
- Features
- Description
- Pin Configuration
- Pin Description: RF Part
- Pin Description: Microcontroller Part
- UHF ASK/FSK Transmitter Block
- Features
- Description
- General Description
- Functional Description
- Absolute Maximum Ratings
- Thermal Resistance
- Electrical Characteristics
- Microcontroller Block
- Features
- Description
- Introduction
- Microcontroller Architecture General Description
- Components of Microcontroller Core
- Master Reset
- Voltage Monitor
- Clock Generation
- Power-down Modes
- Peripheral Modules
- Bi-directional Ports
- Timer 3
- Features
- Timer/Counter Modes
- Timer 3 – Mode 1: Timer/Counter
- Timer 3 – Mode 2: Timer/Counter, External Trigger Restart and External Capture (with T3I Input)
- Timer 3 – Mode 3: Timer/Counter, Internal Trigger Restart and Internal Capture (with TOG2)
- Timer 3 – Mode 4: Timer/Counter
- Timer 3 – Mode 5: Timer/Counter, External Trigger Restart and External Capture (with T3I Input)
- Timer 3 Modulator/Demodulator Modes
- Timer 3 – Mode 6: Carrier Frequency Burst Modulation Controlled by Timer 2 Output Toggle FlipFlo...
- Timer 3 – Mode 7: Carrier Frequency Burst Modulation Controlled by SSI Internal Output (SO)
- Timer 3 – Mode 8: FSK Modulation with Shift Register Data (SO)
- Timer 3 – Mode 9: Pulse-width Modulation with the Shift Register
- Timer 3 – Mode 10: Manchester Demodulation/Pulse-width Demodulation
- Timer 3 – Mode 11: Biphase Demodulation
- Timer 3 – Mode 12: Timer/Counter with External Capture Mode (T3I)
- Timer 3 Modulator for Carrier Frequency Burst Modulation
- Timer 3 Demodulator for Biphase, Manchester and Pulse-width-modulated Signals
- Timer 3 Registers
- Timer 3 Mode Register (T3M)
- Timer 3 Control Register 1 (T3C) Write
- Timer 3 Status Register 1 (T3ST) Read
- Timer 3 Clock Select Register (T3CS)
- Timer 3 Compare- and Compare-mode Register
- Timer 3 Compare-Mode Register 1 (T3CM1)
- Timer 3 Compare Mode Register 2 (T3CM2)
- Timer 3 COmpare Register 1 (T3CO1) Byte Write
- Timer 3 COmpare Register 2 (T3CO2) Byte Write
- Timer 3 Capture Register
- Synchronous Serial Interface (SSI)
- Serial Interface Registers
- Combination Modes
- Absolute Maximum Ratings
- Thermal Resistance
- DC Operating Characteristics
- AC Characteristics
- Crystal Characteristics
- Ordering Information
- Package Information
- Table of Contents

30
T48C862-R8
4590B–4BMCU–02/03
The microcontroller block has various power-down modes. During the sleep mode the
clock for the microcontroller block core is stopped. With the NSTOP-bit in the clock man-
agement register (CM), it is programmable if the clock for the on-chip peripherals is
active or stopped during the sleep mode. If the clock for the core and the peripherals is
stopped, the selected oscillator is switched off. An exception is the 32-kHz oscillator, if it
is selected it runs continuously independent of the NSTOP-bit. If the oscillator is stopped
or the 32-kHz oscillator is selected, power consumption is extremely low.
Table 4. Power-down Modes
Peripheral Modules
Addressing Peripherals Accessing the peripheral modules takes place via the I/O bus (see Figure 21). The IN or
OUT instructions allow direct addressing of up to 16 I/O modules. A dual register
addressing scheme has been adopted to enable direct addressing of the primary regis-
ter. To address the auxiliary register, the access must be switched with an auxiliary
switching module. Thus, a single IN (or OUT) to the module address will read (or write
into) the module primary register. Accessing the auxiliary register is performed with the
same instruction preceded by writing the module address into the auxiliary switching
module. Byte wide registers are accessed by multiple IN- (or OUT-) instructions. For
more complex peripheral modules, with a larger number of registers, extended address-
ing is used. In this case, a bank of up to 16 subport registers are indirectly addressed
with the subport address. The first OUT-instruction writes the subport address to the sub
address register, the second IN- or OUT-instruction reads data from or writes data to the
addressed subport.
Mode
CPU
Core
Osc-
Stop
(1)
Brown-
out
Function
RC-oscillator 1
RC-oscillator 2
4-MHz
Oscillator
32-kHz
Oscillator
External
Input
Clock
Active RUN NO Active RUN RUN YES
Power-
down
SLEEP NO Active RUN RUN YES
SLEEP SLEEP YES STOP STOP RUN STOP
Note: 1. Osc-Stop = SLEEP and NSTOP and WDL










