Owner manual

28
T48C862-R8
4590B–4BMCU–02/03
Figure 25. 32-kHz Crystal Oscillator
Clock Management The clock management register controls the system clock divider and synchronization
stage. Writing to this register triggers the synchronization cycle.
Clock Management Register
(CM)
Auxiliary register address: "3"hex
32-kHz
oscillator
32Out
32Out
OSC1
OSC2
*
Oscin
C1
*
C2
Oscout
XTAL
32 kHz
*
Configurable
Bit 3Bit 2Bit 1Bit 0
CM: NSTOP CCS CSS1 CSS0 Reset value: 1111b
NSTOP Not STOP peripheral clock
NSTOP = 0, stops the peripheral clock while the core is in SLEEP mode
NSTOP = 1, enables the peripheral clock while the core is in SLEEP mode
CCS Core Clock Select
CCS = 1, the internal RC-oscillator 1 generates SYSCL
CCS = 0, the 4-MHz crystal oscillator, the 32-kHz crystal oscillator, an external
clock source or the internal RC-oscillator 2 with the external resistor at OSC1
generates SYSCL dependent on the setting of OS0 and OS1 in the system
configuration register
CSS1 Core Speed Select 1
CSS0 Core Speed Select 0
CSS1 CSS0 Divider Note
0016
118Reset value
104
012