Manual

RF22
Version: 0.1 Date: 12/23/2008
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77
29 pwst[0] internal power state pwst[1] internal power state pwst[2] internal power state
30 xok chip ready: READY
state
pll_en PLL enable: TUNE state
tx_en
TX enable: TX state
31
ts_en
temperature sensor
enable
auto_tx_on
automatic TX ON tx_off TX OFF
32 ch_freq_req frequency change
request
return_tx
return from TX pk_sent packet sent
33
retran_req
retransmission request tx_ffpt_store TX FIFO pointer store tx_ffpt_restore TX FIFO pointer restore
34 pa_on_trig PA ON trigger dly_5us_ok 5 us delay expired mod_dly_ok modulator delay expired
35 tx_shdwn TX shutdown
ramp_start
modulator ramp down
start
ramp_done modulator ramp down
ended
36 pk_sent_dly delayed packet sent tx_shdwn_done TX shutdown done pa_ramp_en PA ramp enable
37 tx_en TX enable: TX state ldo_rf_precharge RF LDO precharge pa_ramp_en PA ramp enable
38 pa_on_trig TX enable: TX state dp_tx_en packet handler (TX)
enable
mod_en modulator enable
39
reg_wr_en
register write enable reg_rd_en register rdead enable addr_inc register address
increment
40 dp_tx_en packet handler (TX)
enable
data_start start of TX data pk_sent packet has been sent
41 data_start start of TX data
tx_out
packet handler TX data
out
pk_sent packet has been sent
42 ramp_done ramp is done data_start start of TX data pk_tx packet is being
transmitted
43 tx_ffaf TX FIFO almost full tx_fifo_wr_en TX FIFO write enable tx_ffem_tst internal TX FIFO empty
44 clk_mod modulator gated 10MHz
clock
tx_clk TX clock from NCO rd_clk_x8 read clock = tx_clk / 10
45 mod_en modulator enable
ramp_start
start modulator ramping
down
ramp_done modulator ramp done
46 data_start data input start from PH ook_en OOK modulation enable ook (also
internal PN9)
OOK modulation
47
prog_req
freq. channel update
request
freq_err wrong freq. indication dsm_rst_s_n dsm sync. reset
48 mod_en modulator enable tx_rdy TX ready tx_clk TX clock from NCO
49 dp_rx_en packet handler (RX)
enable
prea_valid valid preamble pk_srch packet is being
searched
50 pk_srch packet is being
searched
sync_ok sync. word has been
detected
rx_data packet handler RX data
input
51 pk_rx packet is being received sync_ok sync. word has been
detected
pk_valid valid packet received
52 sync_ok sync. word has been
detected
crc_error
CRC error has been
detected
hdch_error header error detected
53 direct_mode direct mode rx_ffaf RX FIFO almost full rx_fifo_rd_en RX FIFO read enable
54 bit_clk bit clock prea_valid valid preamble rx_data demodulator RX data
output
55 prea_valid valid preamble prea_inval invalid preamble ant_div_sw antenna switch
(algorythm)
56 sync_ok sync. word has been
detected
bit_clk bit clock rx_data demodulator RX data
output
57 demod phase[4] demodulator phase
MSB
demod phase [3] demodulator MSB-1 demod phase
[2]
demodulator MSB-2
58 prea_valid valid preamble demod_tst[2] demodulator test demod_tst[1] demodulator test
59 agc_smp_clk AGC sample clock win_h_tp window comparator high win_l_tp window comparator low
dly’d
60 agc_smp_clk AGC sample clock win_h_dly_tp window comparator high win_l_dly_tp window comparator low
dly’d
61 ldc_on active low duty cycle pll_en PLL enable: TUNE state rx_en RX enable: RX state
62 ldc_on active low duty cycle no_sync_det no sync word detected prea_valid valid preamble
63 adc_en ADC enable adc_refdac_en
ADC reference DAC
enable
adc_rst_n combined ADC reset