Manual

RF22
Version: 0.1 Date: 12/23/2008
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75
Register 4Ah. Received Header 0
Bit D7 D6 D5 D4 D3 D2 D1 D0
Name rxhd[7:0]
Type R
Reset value = 00000000
Bit Name Function
7:0 rxhd[7:0] Received Header 0.
1st byte of the received header.
Register 4Bh. Received Packet Length
Bit D7 D6 D5 D4 D3 D2 D1 D0
Name
rxplen[7:0]
Type R
Reset value = 11111111
Bit Name Function
7:0 rxplen[7:0] Length Byte of the Received Packet during fixpklen = 0.
(Specifies the number of Data bytes in the last received packet) This will be relevant ONLY if
fixpklen (address 33h, bit[3]) is low during the receive time. If fixpklen is high, then the number of
received Data Bytes can be read from the pklen register (address h3E).
Register 50h. Analog Test Bus Select
Bit D7 D6 D5 D4 D3 D2 D1 D0
Name Reserved atb[4:0]
Type R/W R/W
Reset value = 00000000
Bit Name Function
7:5 Reserved Reserved.
4:0 atb[4:0] Analog Test Bus.
The selection of internal analog testpoints that are muxed onto TESTp and TESTn.
Internal analog signals available on the Analog Test Bus:
atb[4:0] GPIOx GPIOx atb[4:0] GPIOx GPIOx
1 MixIp MixIn 17 spare spare
2 MixQp MixQn 18 ICP_Test PLL_IBG_05
3 PGA_Ip PGA_In 19 PLL_VBG VSS_VCO
4 PGA_QP PGA_Qn 20 Vctrl_Test PLL_IPTAT_05
5 ADC_vcm ADC_vcmb 21 PA_vbias spare
6 ADC_ipoly10u ADC_ref 22 DIGBG DIGVFB
7 ADC_Refdac_p ADC_Refdac_n 23 IFBG IFVFB
8 ADC_ipoly10 ADC_ipoly10 24 PLLBG PLLVReg
9 ADC_Res1Ip ADC_Res1In 25 IBias10u IBias5u
10 ADC_Res1Qp ADC_Res1Qn 26 32KRC_Ucap 32KRC_Ures
11 spare spare 27 ADC8_VIN ADC8_VDAC
12 spare spare 28 LBDcomp LBDcompref
13 spare spare 29 TSBG TSVtemp
14 spare spare 30 RFBG RFVREG
15 spare spare 31 VCOBG VCOVREG
16 spare spare