Manual

RF22
Version: 0.1 Date: 12/23/2008
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*Note: The threshold can be calculated as Vthreshold = (1.675 + LBDT * 50 mV) ±25 mV.
Register 1Bh. Battery Voltage Level
Bit D7 D6 D5 D4 D3 D2 D1 D0
Name Reserved vbat[4:0]
Type R R
Reset value = xxxxxxxx
Bit Name Function
7:5 Reserved Reserved.
4:0 vbat[4:0] Battery Voltage Level.
The battery voltage is converted by a 5 bit ADC. In Sleep Mode the register is updated in every 1
s. In other states it measures continuously.
Register 1Ch. IF Filter Bandwidth
Bit D7 D6 D5 D4 D3 D2 D1 D0
Name dwn3_bypass
ndec_exp[2:0]
filset[3:0]
Type R/W R/W R/W
Reset value = 00000001
Bit Name Function
7 dwn3_bypass Bypass Decimator by 3 (if set).
6:4 ndec_exp[2:0] IF Filter Decimation Rates.
3:0 filset[3:0] IF Filter Coefficient Sets. Defaults are for Rb = 40 kbps and Fd = 20 kHz so Bw = 80 kHz.
Register 1Dh. AFC Loop Gearshift Override
Bit D7 D6 D5 D4 D3 D2 D1 D0
Name afcbd enafc afcgearh[2:0] afcgearl[2:0]
Type R/W R/W R/W R/W
Reset value = 01000000
Bit Name Function
7 afcbd If set, the tolerated AFC frequency error will be halved.
6 enafc AFC Enable.
5:3 afcgearh[2:0] AFC High Gear Setting.
2:0 afcgearl[2:0] AFC Low Gear Setting.
Register 1Eh. AFC Timing Control
Bit D7 D6 D5 D4 D3 D2 D1 D0
Name Reserved shwait[2:0]
lgwait[2:0]
Type R R/W R/W
Reset value = xx001000
Bit Name Function
7:6 Reserved Reserved.
5:3 shwait[2:0] Short Wait Periods after AFC Correction.
Used before preamble is detected. Short wait = (RegValue+1) x 2Tb. If set to 0 then no AFC
correction will occur before preamble detect, i.e. AFC will be disabled.
2:0 lgwait[2:0] Long Wait Periods after Correction.
Used after preamble detected. Long wait = (RegValue+1) x 2Tb. If set to 0 then no AFC
correction will occur after the preamble detect.
The gear-shift register controls BCR loop gain. Before the preamble is detected, BCR loop gain is as follows: