Manual

RF22
Version: 0.1 Date: 12/23/2008
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Table 35. Interrupt or Status 2 Bit Set/Clear Description
Bit Status Name Set/Clear Conditions
7 iswdet Goes high once the Sync Word is detected. Goes low once we are done receiving the current
packet.
6 ipreaval Goes high once the preamble is detected. Goes low once the sync is detected or the RX wait for
the sync times-out.
5 ipreainval Self cleaning, user should use this as an interrupt source rather than a status.
4 irssi Should remain high as long as the RSSI value is above programmed threshold level
3 iwut Wake time timer interrupt. Use as an interrupt, not as a status.
2 ilbd Low Battery Detect. When a low battery event is been detected this bit will be set to 1. This
interrupt event is saved even if it is not enabled by the mask register bit and causes an interrupt
after it is enabled. Probably the status is cleared once the battery is replaced.
1 ichiprdy Chip ready goes high once we enable the xtal, TX or RX and a settling time for the Xtal clock
elapses. The status stay high unless we go back to Idle mode.
0 ipor Power on status.
Table 36. Detailed Description of Status Registers when not Enabled as Interrupts
Bit Status Name Set/Clear conditions:
7 iswdet Goes high once the Sync Word is detected. Goes low once we are done receiving the current
packet.
6 ipreaval Goes high once the preamble is detected. Goes low once the sync is detected or the RX wait for
the sync times-out.
5 ipreainval Self cleaning, user should use this as an interrupt source rather than a status.
4 irssi Should remain high as long as the RSSI value is above programmed threshold level
3 iwut Wake time timer interrupt. Use as an interrupt, not as a status.
2 ilbd Low Battery Detect. When a low battery event is been detected this bit will be set to 1. This
interrupt event is saved even if it is not enabled by the mask register bit and causes an interrupt
after it is enabled. Probably the status is cleared once the battery is replaced.
1 ichiprdy Chip ready goes high once we enable the xtal, TX or RX and a settling time for the Xtal clock
elapses. The status stay high unless we go back to Idle mode.
0 ipor Power on status.
Register 05h. Interrupt Enable 1
Bit D7 D6 D5 D4 D3 D2 D1 D0
Name enfferr entxffafull entxffaem enrxffafull enext enpksent enpkvalid encrcerror
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset value = 00000000
Bit Name Function
7 enfferr Enable FIFO Underflow/Overflow.
When set to 1 the FIFO Underflow/Overflow interrupt will be enabled.
6 entxffafull Enable TX FIFO Almost Full.
When set to 1 the TX FIFO Almost Full interrupt will be enabled.
5 entxffaem Enable TX FIFO Almost Empty.
When set to 1 the TX FIFO Almost Empty interrupt will be enabled.
4 enrxffafull Enable RX FIFO Almost Full.
When set to 1 the RX FIFO Almost Full interrupt will be enabled.
3 enext Enable External Interrupt.
When set to 1 the External Interrupt will be enabled.
2 enpksent Enable Packet Sent.
When ipksent =1 the Packet Sense Interrupt will be enabled.
1 enpkvalid Enable Valid Packet Received.
When ipkvalid = 1 the Valid Packet Received Interrupt will be enabled
0 encrcerror Enable CRC Error.
When set to 1 the CRC Error interrupt will be enabled.