Manual

RF22
Version: 0.1 Date: 12/23/2008
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55
Table 34. When do the individual Status Bits get Set/Cleared, if not Enabled as an Interrupt?
Bit Status Name Set/Clear Conditions
7 ifferr Set if there is a TX or RX FIFO Overflow or Underflow. It is cleared only by applying FIFO reset to
the specific FIFO that caused the condition.
6 itxffafull Will be set when the number of bytes written to TX FIFO is greater than the Almost Full threshold
set by SPI. It is automatically cleared when we start transmitting and the FIFO data is read out
and the number of bytes left in the FIFO is smaller or equal to the threshold).
5 itxffaem Will be set when the number of bytes (not yet transmitted) in TX FIFO is smaller or equal than the
Almost Empty threshold set by SPI. It is automatically cleared when we write enough data to TX
FIFO so that the number of data bytes not yet transmitted is above the Almost Empty threshold.
4 irxffafull Will be set when the number of bytes received (and not yet read-out) in RX FIFO is greater than
the Almost Full threshold set by SPI. It is automatically cleared when we read enough data from
RX FIFO so that the number of data bytes not yet read is below the Almost Full threshold.
3 iext External interrupt source
2 ipksent Will go high once a packet is sent all the way through (no TX abort). This status will be cleaned if
1) We leave FIFO mode or 2) In FIFO mode we start a new transmission.
1 ipkvalid Goes high once a packet is fully received (no RX abort). It is automatically cleaned once we
receive and acknowledge the Sync Word for the next packet.
0 icrcerror Goes High once the CRC computed during RX differs from the CRC sent in the packet by the TX.
It is cleaned once we start receiving new data in the next packet.
Register 04h. Interrupt/Status 2
Bit D7 D6 D5 D4 D3 D2 D1 D0
Name iswdet ipreaval ipreainval irssi iwut ilbd ichiprdy ipor
Type R R R R R R R R
Reset value = xxxxxxxx
Bit Name Function
7 iswdet Sync Word Detected.
When a sync word is detected this bit will be set to 1.
6 ipreaval Valid Preamble Detected.
When a preamble is detected this bit will be set to 1.
5 ipreainval Invalid Preamble Detected.
When the preamble is not found within a period of time after the RX is enabled, this bit will be set
to 1.
4 irssi RSSI.
When RSSI level exceeds the programmed threshold this bit will be set to 1.
3 iwut
Wake-Up-Timer.
On the expiration of programmed wake-up timer this bit will be set to 1.
2 ilbd Low Battery Detect.
When a low battery event is been detected this bit will be set to 1. This interrupt event is saved
even if it is not enabled by the mask register bit and causes an interrupt after it is enabled.
1 ichiprdy Chip Ready (XTAL).
When a chip ready event has been detected this bit will be set to 1.
0 ipor Power-on-Reset (POR).
When the chip detects a Power on Reset above the desired setting this bit will be set to 1.
When any of the Interrupt/Status Register 2 bits change state from 0 to 1 the control block will notify the microcontroller
by setting the nIRQ pin LOW if it is enabled in the Interrupt Enable 2 register. The nIRQ pin will go to HIGH and all the
enabled interrupt bits will be cleared when the microcontroller reads this address. If any of these bits is not enabled in
the Interrupt Enable 2 register then it becomes a status signal that can be read anytime in the same location and will
not be cleared by reading the register.