Manual

RF22
Version: 0.1 Date: 12/23/2008
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46
47
prog_req
freq. channel update request freq_err wrong freq. indication dsm_rst_s_n dsm sync. reset
48 mod_en modulator enable tx_rdy TX ready tx_clk TX clock from NCO
49 dp_rx_en packet handler (RX) enable prea_valid valid preamble pk_srch packet is being searched
50 pk_srch packet is being searched sync_ok sync. word has been
detected
rx_data packet handler RX data input
51 pk_rx packet is being received sync_ok sync. word has been
detected
pk_valid valid packet received
52 sync_ok sync. word has been detected
crc_error
CRC error has been
detected
hdch_error header error detected
53 direct_mode direct mode rx_ffaf RX FIFO almost full rx_fifo_rd_en RX FIFO read enable
54 bit_clk bit clock prea_valid valid preamble rx_data demodulator RX data output
55 prea_valid valid preamble prea_inval invalid preamble ant_div_sw antenna switch (algorythm)
56 sync_ok sync. word has been detected bit_clk bit clock rx_data demodulator RX data output
57 clk_demod demodulator gated 30 MHz clk adc_lsb_i ADC I channel data LSB demod_tst[0] demodulator test
58 prea_valid valid preamble demod_tst[2] demodulator test demod_tst[1] demodulator test
59 agc_smp_clk AGC sample clock win_h_tp window comparator high win_l_tp window comparator low
delayed
60 agc_smp_clk AGC sample clock win_h_dly_tp window comparator high win_l_dly_tp window comparator low
delayed
61 ldc_on active low duty cycle pll_en PLL enable: TUNE state
rx_en
RX enable: RX state
62 ldc_on active low duty cycle no_sync_det no sync word detected prea_valid valid preamble
63 adc_en ADC enable adc_refdac_en ADC reference DAC enable adc_rst_n combined ADC reset