Owner's manual

RF12
14
Low Battery Detector and
Microcontroller Clock Divider
Command
LBD voltage and microcontroller clock division
ratio
d2 to d0, v4 to
v0
15 Status Read Command Status bits can be read out
In general, setting the given bit to one will activate the related function. In the following tables, the POR
column shows the default values of the command registers after power-on.
Description of the Control Commands
1. Configuration Setting Command
bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
1 0 0 0 0 0 0 0 el ef b1 b0 x3 x2 x1 x0 8008h
Bit el enables the internal data register. If the data register is used the FSK pin must be connected to
logic high level.
Bit ef enables the FIFO mode. If ef=0 then DATA (pin 6) and DCLK (pin 7) are used for data and data
clock output.
b1 b0 Frequency Band {MHz]
0 0 315
0 1 433
1 0 868
1 1 915
x3 x2 x1 x0 Crystal Load Capacitance [pF]
0 0 0 0 8.5
0 0 0 1 9.0
0 0 1 0 9.5
0 0 1 1 10.0
…
1 1 1 0 15.5
1 1 1 1 16.0
2. Power Management Command
bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
1 0 0 0 0 0 1 0 er ebb et es ex eb ew dc 8208h
Bit Function of the control bit Related blocks
er
Enables the whole receiver chain RF front end, baseband,
synthesizer, oscillator
ebb The receiver baseband circuit can be separately switched on Baseband
et
Switches on the PLL, the power amplifier, and starts the
transmission (If TX register is enabled)
Power amplifier, synthesizer,
oscillator
es Turns on the synthesizer Synthesizer
ex Turns on the crystal oscillator Crystal oscillator
eb Enables the low battery detector Low battery detector
ew Enables the wake-up timer Wake-up timer
dc Disables the clock output (pin 8) Clock output buffer
The ebb, es, and ex bits are provided to optimize the TX to RX or RX to TX turnaround time.
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