Manual
Table Of Contents
- 1 GENERAL DESCRIPTION
- 2 FEATURES
- 3 PARTS INFORMATION LIST AND PIN CONFIGURATION
- 4 BLOCK DIAGRAM
- 5 FUNCTIONAL DESCRIPTION
- 5.1 ARM® Cortex™-M0 core
- 5.2 System Manager
- 5.3 Clock Controller
- 5.4 USB Device Controller
- 5.5 General Purpose I/O
- 5.6 I2C Serial Interface Controller (Master/Slave)
- 5.7 PWM Generator and Capture Timer
- 5.8 Real Time Clock (RTC)
- 5.9 Serial Peripheral Interface (SPI) Controller
- 5.10 Timer Controller
- 5.11 Watchdog Timer
- 5.12 UART Interface Controller
- 5.13 Controller Area Network (CAN Bus)
- 5.14 PS2 Device Controller (PS2D)
- 5.15 I2S Controller
- 5.16 Analog-to-Digital Converter (ADC)
- 5.17 Analog Comparator
- 5.18 PDMA Controller
- 6 FLASH MEMORY CONTROLLER (FMC)
- 7 ELECTRICAL CHARACTERISTICS
- 7.1 Absolute Maximum Ratings
- 7.2 DC Electrical Characteristics
- 7.3 AC Electrical Characteristics
- 7.4 Analog Characteristics
- 7.4.1 Specification of 12-bit SARADC
- 7.4.2 Specification of LDO & Power management
- 7.4.3 Specification of Low Voltage Reset
- 7.4.4 Specification of Brownout Detector
- 7.4.5 Specification of Power-On Reset (5V)
- 7.4.6 Specification of Temperature Sensor
- 7.4.7 Specification of Comparator
- 7.4.8 Specification of USB PHY
- 8 PACKAGE DIMENSIONS
- 9 REVISION HISTORY
NUC140 Series DATA SHEET
Publication Release Date: May 31, 2010
- 65 - Revision V1.02
7.4.2 Specification of LDO & Power management
PARAMETER MIN TYP MAX UNIT NOTE
Input Voltage 2.7 5 5.5 V V
DD
input voltage
Output Voltage
(bypass=0)
-10% 2.45 +10% V LDO output voltage
Output Voltage
(bypass=1)
-10% Input
Voltage
+10% V Input Voltage < 2.7V
Temperature -40 25 85 oC
Quiescent Current
(PD=0, bypass=0)
- 100 - uA
Quiescent Current
(PD=1, bypass=0)
- 5 - uA
Quiescent Current
(PD=1, bypass=1)
- 5 - uA
Iload (PD=0) - - 100 mA
Iload (PD=1) - - 100 uA
Cbp - 1u - F Resr=1ohm
Cload - 250p - F
Note:
1. It is recommended that a 10uF or higher capacitor and a 100nF bypass capacitor are connected
between VDD and the closest VSS pin of the device.
2. For ensuring power stability, a 4.7uF or higher capacitor must be connected between LDO pin
and the closest VSS pin of the device. Also a 100nF bypass capacitor between LDO and VSS
help suppressing output noise.