Manual
Table Of Contents
- 1 GENERAL DESCRIPTION
- 2 FEATURES
- 3 PARTS INFORMATION LIST AND PIN CONFIGURATION
- 4 BLOCK DIAGRAM
- 5 FUNCTIONAL DESCRIPTION
- 5.1 ARM® Cortex™-M0 core
- 5.2 System Manager
- 5.3 Clock Controller
- 5.4 USB Device Controller
- 5.5 General Purpose I/O
- 5.6 I2C Serial Interface Controller (Master/Slave)
- 5.7 PWM Generator and Capture Timer
- 5.8 Real Time Clock (RTC)
- 5.9 Serial Peripheral Interface (SPI) Controller
- 5.10 Timer Controller
- 5.11 Watchdog Timer
- 5.12 UART Interface Controller
- 5.13 Controller Area Network (CAN Bus)
- 5.14 PS2 Device Controller (PS2D)
- 5.15 I2S Controller
- 5.16 Analog-to-Digital Converter (ADC)
- 5.17 Analog Comparator
- 5.18 PDMA Controller
- 6 FLASH MEMORY CONTROLLER (FMC)
- 7 ELECTRICAL CHARACTERISTICS
- 7.1 Absolute Maximum Ratings
- 7.2 DC Electrical Characteristics
- 7.3 AC Electrical Characteristics
- 7.4 Analog Characteristics
- 7.4.1 Specification of 12-bit SARADC
- 7.4.2 Specification of LDO & Power management
- 7.4.3 Specification of Low Voltage Reset
- 7.4.4 Specification of Brownout Detector
- 7.4.5 Specification of Power-On Reset (5V)
- 7.4.6 Specification of Temperature Sensor
- 7.4.7 Specification of Comparator
- 7.4.8 Specification of USB PHY
- 8 PACKAGE DIMENSIONS
- 9 REVISION HISTORY
NUC140 Series DATA SHEET
Publication Release Date: May 31, 2010
- 6 - Revision V1.02
2 FEATURES
• Core
– ARM® Cortex™-M0 core runs up to 50MHz.
– One 24-bit system timer.
– Supports low power sleep-mode.
– Single-cycle 32-bit hardware multiplier.
– NVIC for the 32 interrupt inputs, each with 4-levels of priority.
– Serial Wire Debug supports with 2 watchpoints/4 breakpoints.
• Wide operating voltage ranges from 2.5V to 5.5V
• Flash EPROM Memory
– 64K/128K bytes Flash EPROM for program code.
– 4kB flash for ISP loader
– Support In-system program(ISP) and In-application program(IAP) application code update
– 512 byte page erase for flash
– Configurable data flash address and size for 128kB system, fixed 4kB data flash for 64kB
system.
– Support 2-wire ICP update from ICE interface
– Support fast parallel programming mode by external programmer.
• SRAM Memory
– 8K/16k bytes embedded SRAM.
– Support PDMA mode
• PDMA (Peripheral DMA)
– Support 9 channels PDMA for automatic data transfer between SRAM and peripherals.
• Clock Control
– Flexible selection for different applications.
– Build-in 22MHz OSC (Trimmed to 1%) for system operation, and low power 10KHz OSC for
watchdog and wakeup sleep operation.
– Support one PLL, up to 50MHz, for high performance system operation.
– External 12MHz crystal input for USB and precise timing operation.
– External 32 kHz crystal input for RTC function and low power system operation.
• GPIO
– Four I/O modes:
Quasi bi-direction
Push-Pull output
Open-Drain output
Input only with high impendence
– TTL/Schmitt trigger input selectable.
– I/O pin can be configured as interrupt source with edge/level setting.
– High driver and high sink IO mode support.