Manual
Table Of Contents
- 1 GENERAL DESCRIPTION
- 2 FEATURES
- 3 PARTS INFORMATION LIST AND PIN CONFIGURATION
- 4 BLOCK DIAGRAM
- 5 FUNCTIONAL DESCRIPTION
- 5.1 ARM® Cortex™-M0 core
- 5.2 System Manager
- 5.3 Clock Controller
- 5.4 USB Device Controller
- 5.5 General Purpose I/O
- 5.6 I2C Serial Interface Controller (Master/Slave)
- 5.7 PWM Generator and Capture Timer
- 5.8 Real Time Clock (RTC)
- 5.9 Serial Peripheral Interface (SPI) Controller
- 5.10 Timer Controller
- 5.11 Watchdog Timer
- 5.12 UART Interface Controller
- 5.13 Controller Area Network (CAN Bus)
- 5.14 PS2 Device Controller (PS2D)
- 5.15 I2S Controller
- 5.16 Analog-to-Digital Converter (ADC)
- 5.17 Analog Comparator
- 5.18 PDMA Controller
- 6 FLASH MEMORY CONTROLLER (FMC)
- 7 ELECTRICAL CHARACTERISTICS
- 7.1 Absolute Maximum Ratings
- 7.2 DC Electrical Characteristics
- 7.3 AC Electrical Characteristics
- 7.4 Analog Characteristics
- 7.4.1 Specification of 12-bit SARADC
- 7.4.2 Specification of LDO & Power management
- 7.4.3 Specification of Low Voltage Reset
- 7.4.4 Specification of Brownout Detector
- 7.4.5 Specification of Power-On Reset (5V)
- 7.4.6 Specification of Temperature Sensor
- 7.4.7 Specification of Comparator
- 7.4.8 Specification of USB PHY
- 8 PACKAGE DIMENSIONS
- 9 REVISION HISTORY
NUC140 Series DATA SHEET
Publication Release Date: May 31, 2010
- 55 - Revision V1.02
6 FLASH MEMORY CONTROLLER (FMC)
6.1 Overview
NUC1XX series equips with 128/64/32K bytes on chip embedded Flash EEPROM for application
program memory (APROM) that can be updated through ISP/IAP procedure. In System Programming
(ISP) function enables user to update program memory when chip is soldered on PCB. After chip
power on Cortex-M0 CPU fetches code from APROM or LDROM decided by boot select (CBS) in
Config0. By the way, NUC1XX series also provide additional 4k bytes DATA Flash for user, to store
some application dependent data before chip power off, in 64/32k APROM model. For 128k bytes
device, the data flash is shared with original 128k program memory and its start address is
configurable and defined by user in Config1. The data flash size is defined by user depends on her
application request.
6.2 Features
y AHB interface compatible
y Run up to 50 MHz with zero wait state for discontinuous address read access
y 128/64/32KB application program memory (APROM)
y 4KB in system programming (ISP) loader program memory (LDROM)
y Configurable or fixed 4KB data flash with 512 bytes page erase unit
y Programmable data flash start address and memory size for 128K program memory
y In System Program (ISP)/In Application Program (IAP) to update on chip Flash EPROM