Manual
Table Of Contents
- 1 GENERAL DESCRIPTION
- 2 FEATURES
- 3 PARTS INFORMATION LIST AND PIN CONFIGURATION
- 4 BLOCK DIAGRAM
- 5 FUNCTIONAL DESCRIPTION
- 5.1 ARM® Cortex™-M0 core
- 5.2 System Manager
- 5.3 Clock Controller
- 5.4 USB Device Controller
- 5.5 General Purpose I/O
- 5.6 I2C Serial Interface Controller (Master/Slave)
- 5.7 PWM Generator and Capture Timer
- 5.8 Real Time Clock (RTC)
- 5.9 Serial Peripheral Interface (SPI) Controller
- 5.10 Timer Controller
- 5.11 Watchdog Timer
- 5.12 UART Interface Controller
- 5.13 Controller Area Network (CAN Bus)
- 5.14 PS2 Device Controller (PS2D)
- 5.15 I2S Controller
- 5.16 Analog-to-Digital Converter (ADC)
- 5.17 Analog Comparator
- 5.18 PDMA Controller
- 6 FLASH MEMORY CONTROLLER (FMC)
- 7 ELECTRICAL CHARACTERISTICS
- 7.1 Absolute Maximum Ratings
- 7.2 DC Electrical Characteristics
- 7.3 AC Electrical Characteristics
- 7.4 Analog Characteristics
- 7.4.1 Specification of 12-bit SARADC
- 7.4.2 Specification of LDO & Power management
- 7.4.3 Specification of Low Voltage Reset
- 7.4.4 Specification of Brownout Detector
- 7.4.5 Specification of Power-On Reset (5V)
- 7.4.6 Specification of Temperature Sensor
- 7.4.7 Specification of Comparator
- 7.4.8 Specification of USB PHY
- 8 PACKAGE DIMENSIONS
- 9 REVISION HISTORY
NUC140 Series DATA SHEET
Publication Release Date: May 31, 2010
- 54 - Revision V1.02
5.18 PDMA Controller
5.18.1 Overview
The NUC1XX contains a peripheral direct memory access (PDMA) controller that transfers data to and
from memory or transfer data to and from APB devices. The PDMA has nine channels of DMA
(Peripheral-to-Memory or Memory-to-Peripheral or Memory-to-Memory). For each PDMA channel
(PDMA CH0~CH8), there is one word buffer as transfer buffer between the Peripherals APB devices
and Memory.
Software can stop the PDMA operation by disable PDMA [PDMACEN]. The CPU can recognize the
completion of a PDMA operation by software polling or when it receives an internal PDMA interrupt.
The NUC1XX PDMA controller can increment source or destination address, fixed or wrap around
them as well.
5.18.2 Features
y AMBA AHB master/slave interface compatible, for data transfer and register read/write.
y PDMA support 32-bit source and destination addressing range address increment, fixed and
wrap around.