Manual
Table Of Contents
- 1 GENERAL DESCRIPTION
- 2 FEATURES
- 3 PARTS INFORMATION LIST AND PIN CONFIGURATION
- 4 BLOCK DIAGRAM
- 5 FUNCTIONAL DESCRIPTION
- 5.1 ARM® Cortex™-M0 core
- 5.2 System Manager
- 5.3 Clock Controller
- 5.4 USB Device Controller
- 5.5 General Purpose I/O
- 5.6 I2C Serial Interface Controller (Master/Slave)
- 5.7 PWM Generator and Capture Timer
- 5.8 Real Time Clock (RTC)
- 5.9 Serial Peripheral Interface (SPI) Controller
- 5.10 Timer Controller
- 5.11 Watchdog Timer
- 5.12 UART Interface Controller
- 5.13 Controller Area Network (CAN Bus)
- 5.14 PS2 Device Controller (PS2D)
- 5.15 I2S Controller
- 5.16 Analog-to-Digital Converter (ADC)
- 5.17 Analog Comparator
- 5.18 PDMA Controller
- 6 FLASH MEMORY CONTROLLER (FMC)
- 7 ELECTRICAL CHARACTERISTICS
- 7.1 Absolute Maximum Ratings
- 7.2 DC Electrical Characteristics
- 7.3 AC Electrical Characteristics
- 7.4 Analog Characteristics
- 7.4.1 Specification of 12-bit SARADC
- 7.4.2 Specification of LDO & Power management
- 7.4.3 Specification of Low Voltage Reset
- 7.4.4 Specification of Brownout Detector
- 7.4.5 Specification of Power-On Reset (5V)
- 7.4.6 Specification of Temperature Sensor
- 7.4.7 Specification of Comparator
- 7.4.8 Specification of USB PHY
- 8 PACKAGE DIMENSIONS
- 9 REVISION HISTORY
NUC140 Series DATA SHEET
Publication Release Date: May 31, 2010
- 45 - Revision V1.02
5.11 Watchdog Timer
The purpose of Watchdog Timer is to perform a system reset after the software running into a
problem. This prevents system from hanging for an infinite period of time. Besides, this Watchdog
Timer supports the function to wakeup CPU from power-down mode. The watchdog timer includes a
19-bit free running counter with programmable time-out intervals.
Setting WTE (WDTCR[7]) enables the watchdog timer and the WDT counter starts counting up. When
the counter reaches the selected time-out interval, Watchdog timer interrupt flag WTIF will be set
immediately to request a WDT interrupt if the watchdog timer interrupt enable bit WTIE is set, in the
meanwhile, a specified delay time follows the time-out event. User must set WTR (WDTCR[0])
(Watchdog timer reset) high to reset the 19-bit WDT counter to avoid CPU from Watchdog timer reset
before the delay time expires. WTR bit is auto cleared by hardware after WDT counter is reset. There
are eight time-out intervals with specific delay time which are selected by Watchdog timer interval
select bits WTIS (WDTCR[10:8]). If the WDT counter has not been cleared after the specific delay
time expires, the watchdog timer will set Watchdog Timer Reset Flag (WTRF) high and reset CPU.
This reset will last 64 WDT clocks then CPU restarts executing program from reset vector (0x0000
0000). WTRF will not be cleared by Watchdog reset. User may poll WTFR by software to recognize
the reset source.
Table 5-3 Watchdog Timeout Interval Selection
WTIS
Interrupt
Timeout
Watchdog Reset
Timeout
WTR Timeout Interval
(WDT_CLK=12 MHz)
WTR Timeout Interval
(WDT_CLK=32kHz)
000 2
4
WDT_CLK (2
4
+ 1024) WDT_CLK 69.33 us 31.7 ms
001 2
6
WDT_CLK (2
6
+ 1024) WDT_CLK 72.53 us 33.2 ms
010 2
8
WDT_CLK (2
8
+ 1024) WDT_CLK 85.33 us 39 ms
011 2
10
WDT_CLK (2
10
+ 1024) WDT_CLK 170.67 us 64 ms
100 2
12
WDT_CLK (2
12
+ 1024) WDT_CLK 426.67 us 160 ms
101 2
14
WDT_CLK (2
14
+ 1024) WDT_CLK 1.45 ms 544 ms
110 2
16
WDT_CLK (2
16
+ 1024) WDT_CLK 5.55 ms 2080 ms
111 2
18
WDT_CLK (2
18
+ 1024) WDT_CLK 21.93 ms 8224 ms