Manual
Table Of Contents
- 1 GENERAL DESCRIPTION
- 2 FEATURES
- 3 PARTS INFORMATION LIST AND PIN CONFIGURATION
- 4 BLOCK DIAGRAM
- 5 FUNCTIONAL DESCRIPTION
- 5.1 ARM® Cortex™-M0 core
- 5.2 System Manager
- 5.3 Clock Controller
- 5.4 USB Device Controller
- 5.5 General Purpose I/O
- 5.6 I2C Serial Interface Controller (Master/Slave)
- 5.7 PWM Generator and Capture Timer
- 5.8 Real Time Clock (RTC)
- 5.9 Serial Peripheral Interface (SPI) Controller
- 5.10 Timer Controller
- 5.11 Watchdog Timer
- 5.12 UART Interface Controller
- 5.13 Controller Area Network (CAN Bus)
- 5.14 PS2 Device Controller (PS2D)
- 5.15 I2S Controller
- 5.16 Analog-to-Digital Converter (ADC)
- 5.17 Analog Comparator
- 5.18 PDMA Controller
- 6 FLASH MEMORY CONTROLLER (FMC)
- 7 ELECTRICAL CHARACTERISTICS
- 7.1 Absolute Maximum Ratings
- 7.2 DC Electrical Characteristics
- 7.3 AC Electrical Characteristics
- 7.4 Analog Characteristics
- 7.4.1 Specification of 12-bit SARADC
- 7.4.2 Specification of LDO & Power management
- 7.4.3 Specification of Low Voltage Reset
- 7.4.4 Specification of Brownout Detector
- 7.4.5 Specification of Power-On Reset (5V)
- 7.4.6 Specification of Temperature Sensor
- 7.4.7 Specification of Comparator
- 7.4.8 Specification of USB PHY
- 8 PACKAGE DIMENSIONS
- 9 REVISION HISTORY
NUC140 Series DATA SHEET
Publication Release Date: May 31, 2010
- 44 - Revision V1.02
5.10 Timer Controller
5.10.1 General Timer Controller
The timer module includes four channels, TIMER0~TIMER3 (TIMER0 and TIMER1 are at APB1 and
TIMER2 and TIMER3 are at APB2), which allow user to easily implement a counting scheme or timing
control for applications. The timer can perform functions like frequency measurement, event counting,
interval measurement, clock generation, delay timing, and so on. The timer can generates an interrupt
signal upon timeout, or provide the current value of count during operation.
5.10.2 Features
y Independent clock source for each channel (TMR0_CLK, TMR1_CLK, TMR2_CLK, TMR3_CLK).
y Time out period = (Period of timer clock input) * (8-bit Prescale + 1) * (24-bit TCMP)
y Maximum counting cycle time = (1 / 25 MHz) * (2^8) * (2^24), if TCLK = 25 MHz.
y Internal 24-bit up counter is readable through TDR (Timer Data Register).