Manual
Table Of Contents
- 1 GENERAL DESCRIPTION
- 2 FEATURES
- 3 PARTS INFORMATION LIST AND PIN CONFIGURATION
- 4 BLOCK DIAGRAM
- 5 FUNCTIONAL DESCRIPTION
- 5.1 ARM® Cortex™-M0 core
- 5.2 System Manager
- 5.3 Clock Controller
- 5.4 USB Device Controller
- 5.5 General Purpose I/O
- 5.6 I2C Serial Interface Controller (Master/Slave)
- 5.7 PWM Generator and Capture Timer
- 5.8 Real Time Clock (RTC)
- 5.9 Serial Peripheral Interface (SPI) Controller
- 5.10 Timer Controller
- 5.11 Watchdog Timer
- 5.12 UART Interface Controller
- 5.13 Controller Area Network (CAN Bus)
- 5.14 PS2 Device Controller (PS2D)
- 5.15 I2S Controller
- 5.16 Analog-to-Digital Converter (ADC)
- 5.17 Analog Comparator
- 5.18 PDMA Controller
- 6 FLASH MEMORY CONTROLLER (FMC)
- 7 ELECTRICAL CHARACTERISTICS
- 7.1 Absolute Maximum Ratings
- 7.2 DC Electrical Characteristics
- 7.3 AC Electrical Characteristics
- 7.4 Analog Characteristics
- 7.4.1 Specification of 12-bit SARADC
- 7.4.2 Specification of LDO & Power management
- 7.4.3 Specification of Low Voltage Reset
- 7.4.4 Specification of Brownout Detector
- 7.4.5 Specification of Power-On Reset (5V)
- 7.4.6 Specification of Temperature Sensor
- 7.4.7 Specification of Comparator
- 7.4.8 Specification of USB PHY
- 8 PACKAGE DIMENSIONS
- 9 REVISION HISTORY

NUC140 Series DATA SHEET
Publication Release Date: May 31, 2010
- 43 - Revision V1.02
5.9 Serial Peripheral Interface (SPI) Controller
5.9.1 Overview
The Serial Peripheral Interface (SPI) is a synchronous serial data communication protocol which
operates in full duplex mode. Devices communicate in master/slave mode with 4-wire bi-direction
interface. NUC1XX series contain up to four sets of SPI controller performing a serial-to-parallel
conversion on data received from a peripheral device, and a parallel-to-serial conversion on data
transmitted to a peripheral device. Each set of SPI controller can be set as a master that can drive up
to 2 external peripheral slave devices; it also can be set as a slave controlled by an off-chip master
device.
5.9.2 Features
y Four sets of SPI controller
y Support master or slave operation
y Support 1 and 2-bit serial data IN/OUT
y Configurable data length of transfer word up to 32 bits
y Variable output serial clock frequency in master mode
y Provide burst mode operation, transmit/receive can be executed up to two times in one transfer
y MSB or LSB first data transfer
y 2 slave/device select lines when it is set as the master mode, and 1 slave/device select line
when it is set as slave mode
y Fully static synchronous design with one clock domain
y Byte Suspend Sleep Mode
y Support two programmable serial output clock frequency.










