Manual
Table Of Contents
- 1 GENERAL DESCRIPTION
- 2 FEATURES
- 3 PARTS INFORMATION LIST AND PIN CONFIGURATION
- 4 BLOCK DIAGRAM
- 5 FUNCTIONAL DESCRIPTION
- 5.1 ARM® Cortex™-M0 core
- 5.2 System Manager
- 5.3 Clock Controller
- 5.4 USB Device Controller
- 5.5 General Purpose I/O
- 5.6 I2C Serial Interface Controller (Master/Slave)
- 5.7 PWM Generator and Capture Timer
- 5.8 Real Time Clock (RTC)
- 5.9 Serial Peripheral Interface (SPI) Controller
- 5.10 Timer Controller
- 5.11 Watchdog Timer
- 5.12 UART Interface Controller
- 5.13 Controller Area Network (CAN Bus)
- 5.14 PS2 Device Controller (PS2D)
- 5.15 I2S Controller
- 5.16 Analog-to-Digital Converter (ADC)
- 5.17 Analog Comparator
- 5.18 PDMA Controller
- 6 FLASH MEMORY CONTROLLER (FMC)
- 7 ELECTRICAL CHARACTERISTICS
- 7.1 Absolute Maximum Ratings
- 7.2 DC Electrical Characteristics
- 7.3 AC Electrical Characteristics
- 7.4 Analog Characteristics
- 7.4.1 Specification of 12-bit SARADC
- 7.4.2 Specification of LDO & Power management
- 7.4.3 Specification of Low Voltage Reset
- 7.4.4 Specification of Brownout Detector
- 7.4.5 Specification of Power-On Reset (5V)
- 7.4.6 Specification of Temperature Sensor
- 7.4.7 Specification of Comparator
- 7.4.8 Specification of USB PHY
- 8 PACKAGE DIMENSIONS
- 9 REVISION HISTORY
NUC140 Series DATA SHEET
5.5.1.3 Open-Drain Mode Explanation
Set GPIOx_PMD (PMDn[1:0]) to 10b the GPIOx port [n] pin is in Open-Drain mode and the I/O pin
supports digital output function but only with sink current capability, an additional pull-up resister is
needed for driving high state. If the bit value in the corresponding bit [n] of GPIOx_DOUT is “0”, the pin
drive a “low” output on the pin. If the bit value in the corresponding bit [n] of GPIOx_DOUT is “1”, the
pin output drives high that is controlled by the internal pull-up resistor or the external pull high resistor.
Port Pin
Port Latch
Data
N
Input Data
Figure 5-9 Open-Drain Output
5.5.1.4 Quasi-bidirectional Mode Explanation
Set GPIOx_PMD (PMDn[1:0]) to 11b the GPIOx port [n] pin is in Quasi-bidirectional mode and the I/O
pin supports digital output and input function at the same time but the source current is only up to
hundreds uA. Before the digital input function is performed the corresponding bit in GPIOx_DOUT
must be set to 1. The quasi-bidirectional output is common on the 80C51 and most of its derivatives. If
the bit value in the corresponding bit [n] of GPIOx_DOUT is “0”, the pin drive a “low” output on the pin.
If the bit value in the corresponding bit [n] of GPIOx_DOUT is “1”, the pin will check the pin value. If
pin value is high, no action takes. If pin state is low, then pin will drive strong high with 2 clock cycles
on the pin and then disable the strong output drive and then the pin status is control by internal pull-up
resistor. Note that the source current capability in quasi-bidirectional mode is only about 200uA to
30uA for VDD is form 5.0V to 2.5V
Port Pin
2 CPU
Clock Delay
Input Data
Port Latch
Data
PP P
N
VDD
Strong
Very
Weak
Weak
Figure 5-10 Quasi-bidirectional I/O Mode
Publication Release Date: May 31, 2010
- 37 - Revision V1.02