Manual
Table Of Contents
- 1 GENERAL DESCRIPTION
- 2 FEATURES
- 3 PARTS INFORMATION LIST AND PIN CONFIGURATION
- 4 BLOCK DIAGRAM
- 5 FUNCTIONAL DESCRIPTION
- 5.1 ARM® Cortex™-M0 core
- 5.2 System Manager
- 5.3 Clock Controller
- 5.4 USB Device Controller
- 5.5 General Purpose I/O
- 5.6 I2C Serial Interface Controller (Master/Slave)
- 5.7 PWM Generator and Capture Timer
- 5.8 Real Time Clock (RTC)
- 5.9 Serial Peripheral Interface (SPI) Controller
- 5.10 Timer Controller
- 5.11 Watchdog Timer
- 5.12 UART Interface Controller
- 5.13 Controller Area Network (CAN Bus)
- 5.14 PS2 Device Controller (PS2D)
- 5.15 I2S Controller
- 5.16 Analog-to-Digital Converter (ADC)
- 5.17 Analog Comparator
- 5.18 PDMA Controller
- 6 FLASH MEMORY CONTROLLER (FMC)
- 7 ELECTRICAL CHARACTERISTICS
- 7.1 Absolute Maximum Ratings
- 7.2 DC Electrical Characteristics
- 7.3 AC Electrical Characteristics
- 7.4 Analog Characteristics
- 7.4.1 Specification of 12-bit SARADC
- 7.4.2 Specification of LDO & Power management
- 7.4.3 Specification of Low Voltage Reset
- 7.4.4 Specification of Brownout Detector
- 7.4.5 Specification of Power-On Reset (5V)
- 7.4.6 Specification of Temperature Sensor
- 7.4.7 Specification of Comparator
- 7.4.8 Specification of USB PHY
- 8 PACKAGE DIMENSIONS
- 9 REVISION HISTORY
NUC140 Series DATA SHEET
Publication Release Date: May 31, 2010
- 34 - Revision V1.02
5.4 USB Device Controller
5.4.1 Overview
NUC1XX series contain one set of USB 2.0 full-speed device controller and transceiver. It is compliant
with USB 2.0 full speed device specification and support control/bulk/interrupt/isochronous transfer
types.
In this device controller, it contains two main interfaces: the AHB bus and USB bus which comes from
the USB PHY transceiver. For the AHB bus, only the slave interface is implemented and the CPU will
program control registers through it. There are 512 bytes internal SRAM as data buffer in this
controller. For IN or OUT transfer, it is necessary to write data to SRAM or read data from SRAM
through the AHB slave interface or SIE. Users need to set the effective starting address of SRAM for
each endpoint buffer through “buffer segmentation register (BUFSEGx)”.
This device controller contains 6 configurable endpoints. Each endpoint needs to be configured
properly in advance for its attribution (IN, OUT or ISO state) & endpoint number. The transmit length in
each endpoint is defined in maximum payload register (MXPLDx). Note that most handshakes
between Host and Device are handled by hardware. Any USB event will cause an interrupt, and users
just need to check the related event flags in interrupt event flag register (EVF) to acknowledge what
kind of events occurring and store the required data into buffer, which is then sent to host by
hardware.
A software-disable function is also available for this USB device, which simulates the disconnection of
this device from the host.
5.4.2 Features
This Universal Serial Bus (USB) performs a serial interface with a single connector type for attaching
all USB peripherals to the host system. Following is the feature list of this USB.
y Compliant with USB 2.0 Full-Speed specification.
y Provide 1 interrupt vector with 4 different interrupt events.
y Support Control/Bulk/Interrupt/Isochronous transfer type.
y Support suspend function when no bus activity showing for 3 ms.
y Provide 6 endpoints for configurable Control/Bulk/Interrupt/Isochronous transfer types and
maximum 512 bytes buffer size.
y Provide remote wakeup capability.