Manual

NUC140 Series DATA SHEET
5.3.5 Frequency Divider Output
This device is equipped a power-of-2 frequency divider which is composed by16 chained divide-by-2
shift registers. One of the 16 shift register outputs selected by a sixteen to one multiplexer is reflected
to GPIOB.12. Therefore there are 16 options of power-of-2 divided clocks with the frequency from
F
in
/2
1
to F
in
/2
16
where Fin is input clock frequency to the clock divider.
The output formula is F
out
= F
in
/2
(N+1)
, where F
in
is the input clock frequency, F
out
is the clock divider
output frequency and N is the 4-bit value in FREQDIV.FSEL[3:0].
When FREQDIV.FDIV_EN[4] is set to high, the rising transition will reset the chained counter and
starts it counting. When FREQDIV.FDIV_EN[4] is written with a zero, the chained counter continuously
runs till divided clock reaches low state and stay in low state.
11
10
01
00
HCLK
32K
12M
22M
CLKSEL2.FRQDIV_S[3:2]
APBCLK.FRQDIV_EN[6]
FRQDIV_CLK
Figure 5-5 Clock Source of Frequency Divider
16 chained
divide-by-2 counter
1/2 …...1/2
2
1/2
3
1/2
15
1/2
16
000
001
110
111
FREQDIV.FSEL[3:0]
:
:
16 to 1
MUX
FREQDIV.FDIV_EN[4]
0 to 1
Reset Clock
Divider
1
0
GPIOB_MFP[12]
& ALT_MPF.PB12_CLKO=1
PB.12/CPO0/
CLKO
GPIOB_DOUT[12]
FRQDIV_CLK
Figure 5-6 Block Diagram of Frequency Divider
Publication Release Date: May 31, 2010
- 33 - Revision V1.02