Manual
Table Of Contents
- 1 GENERAL DESCRIPTION
- 2 FEATURES
- 3 PARTS INFORMATION LIST AND PIN CONFIGURATION
- 4 BLOCK DIAGRAM
- 5 FUNCTIONAL DESCRIPTION
- 5.1 ARM® Cortex™-M0 core
- 5.2 System Manager
- 5.3 Clock Controller
- 5.4 USB Device Controller
- 5.5 General Purpose I/O
- 5.6 I2C Serial Interface Controller (Master/Slave)
- 5.7 PWM Generator and Capture Timer
- 5.8 Real Time Clock (RTC)
- 5.9 Serial Peripheral Interface (SPI) Controller
- 5.10 Timer Controller
- 5.11 Watchdog Timer
- 5.12 UART Interface Controller
- 5.13 Controller Area Network (CAN Bus)
- 5.14 PS2 Device Controller (PS2D)
- 5.15 I2S Controller
- 5.16 Analog-to-Digital Converter (ADC)
- 5.17 Analog Comparator
- 5.18 PDMA Controller
- 6 FLASH MEMORY CONTROLLER (FMC)
- 7 ELECTRICAL CHARACTERISTICS
- 7.1 Absolute Maximum Ratings
- 7.2 DC Electrical Characteristics
- 7.3 AC Electrical Characteristics
- 7.4 Analog Characteristics
- 7.4.1 Specification of 12-bit SARADC
- 7.4.2 Specification of LDO & Power management
- 7.4.3 Specification of Low Voltage Reset
- 7.4.4 Specification of Brownout Detector
- 7.4.5 Specification of Power-On Reset (5V)
- 7.4.6 Specification of Temperature Sensor
- 7.4.7 Specification of Comparator
- 7.4.8 Specification of USB PHY
- 8 PACKAGE DIMENSIONS
- 9 REVISION HISTORY
NUC140 Series DATA SHEET
5 FUNCTIONAL DESCRIPTION
5.1 ARM
®
Cortex™-M0 core
The Cortex™-M0 processor is a configurable, multistage, 32-bit RISC processor. It has an AMBA
AHB-Lite interface and includes an NVIC component. It also has optional hardware debug
functionality. The processor can execute Thumb code and is compatible with other Cortex-M profile
processor.
Figure 5-1 shows the functional blocks of processor.
Publication Release Date: May 31, 2010
- 22 - Revision V1.02
Cortex-M0
Processor
core
Nested
Vectored
Interrupt
Controller
(NVIC)
Breakpoint
and
Watchpoint
unit
Debugger
interface
Bus matrix
Debug
Access Port
(DAP)
DebugCortex-M0 processor
Cortex-M0 components
Interrupts
Wakeup
Interrupt
Controller
(WIC)
Serial Wire or
JTAG debug port
AHB-Lite interface
Figure 5-1 Functional Block Diagram
The implemented device provides:
• A low gate count processor that features:
– The ARMv6-M Thumb® instruction set.
– Thumb-2 technology.
– ARMv6-M compliant 24-bit SysTick timer.
– A 32-bit hardware multiplier.
– The system interface supports little-endian data accesses.
– The ability to have deterministic, fixed-latency, interrupt handling.
– Load/store-multiples and multicycle-multiplies that can be abandoned and restarted to facilitate
rapid interrupt handling.
– C Application Binary Interface compliant exception model.
This is the ARMv6-M, C Application Binary Interface(C-ABI) compliant exception model that
enables the use of pure C functions as interrupt handlers.
– Low power sleep-mode entry using Wait For Interrupt(WFI), Wait For Even(WFE) instructions,
or the return from interrupt sleep-on-exit feature.
• NVIC that features:
– 32 external interrupt inputs, each with four levels of priority.