Instruction Manual

NUC130 Series DATA SHEET

5.3.2 System Clock & SysTick Clock

The system clock has 5 clock sources which were generated from clock generator block. The clock

source switch depends on the register HCLK_S(CLKSEL0[2:0]). The block diagram lists below.

011

010

001

000

1xx

10K

PLLFOUT

32K

12M

22M

HCLK_S(CLKSEL0[2:0])

CPU in Power Down Mode

1/(HCLK_N+1)

HCLK_N(CLKDIV[3:0])

HCLK

CPUCLK

PCLK

CPU

AHB

APB

Figure 5-3 System Clock Block Diagram

The SysTick clock(STCLK) has 5 clock sources which were generated from clock generator block.

The clock source switch depends on the setting of the register STCLK_S(CLKSEL0[5:3]. The block

diagram lists below.

STCLK

011

010

001

000

1xx

HCLK

12M

32K

12M

22M

STCLK_S(CLKSEL0[5:3])

1/2

Figure 5-4 SysTick clock Control Block Diagram

Publication Release Date: May 31, 2010

- 31 - Revision V1.02