Manual

MAX8710/MAX8711/MAX8712
Low-Cost Linear-Regulator
LCD Panel Power Supplies
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1. V
IN
= V
INL
= V
SUPCP
= 12V, V
OUTL
= V
SUPB
= 10V, V
SRC
= 27V, T
A
= 0°C to +85°C. Typical values are at T
A
=
+25°C, unless otherwise noted.)
PARAMETER CONDITIONS
MIN
MAX
UNITS
Common-Mode Input Range V
NEGB
, V
POSB
0
V
SUPB
V
Common-Mode Rejection Ratio 0 (V
NEGB
, V
POSB
) < V
SUPB
50 90 dB
Open-Loop Gain
125
dB
I
OUTB
= 100µA
V
SUPB
-
15
V
SUPB
- 2
Output Voltage Swing High
I
OUTB
= 5mA
V
SUPB
-
150
V
SUPB
- 80
mV
I
OUTB
= -100µA 2 15
Output Voltage Swing Low
I
OUTB
= -5mA 80 150
mV
Short to V
SUPB
/ 2, sourcing 50
150
Short-Circuit Current
Short to V
SUPB
/ 2, sinking 50
140
mA
Output Current
Buffer configuration, V
POSB
= 4V,
V
OUTB
error < ±10mV
±40
mA
Power-Supply Rejection Ratio
6V V
SUPB
13.2V, DC (V
NEGB
, V
POSB
) = V
SUPB
/ 2
60
100
dB
Slew Rate 12 V/µs
-3dB Bandwidth Buffer configuration, R
L
= 10k, C
L
= 10pF 12
MHz
Gain-Bandwidth Product Buffer configuration, R
L
= 10k, C
L
= 10pF 8
MHz
POSITIVE CHARGE-PUMP REGULATOR
FBP Regulation Voltage I
GON
= 10mA
2.425 2.500 2.575
V
FBP Line-Regulation Error
V
OUTL
(V
SUPCP
, MAX8710) = 10.8V~13.2V,
V
GON
= 27V, I
GON
= 20mA
25 mV
FBP Input Bias Current V
FBP
= 2.5V -50
+50
nA
DRVP P-Channel On-Resistance 15 30
V
FBP
= 2.4V 6 12
DRVP N-Channel On-Resistance
V
FBP
= 2.6V 20 k
FBP Fault Trip Level Falling edge
1.92 2.00 2.08
V
Positive Charge-Pump Soft-Start
Period
2
12
oscillator clock cycles in a 7-bit DAC
2.73
ms
NEGATIVE CHARGE-PUMP REGULATOR
FBN Regulation Voltage I
GOFF
= 10mA
200 250
300 mV
FBN Input Bias Current V
FBN
= 250mV -50
+50
nA
FBN Line Regulation
V
OUTL
(V
SUPCP
, MAX8710)
= 10.8V~13.2V,
V
VGOFF
= -6V, I
GOFF
= -50mA
25 mV
DRVN P-Channel On-Resistance 7.5 15
V
FBN
= 350mV 3 6
DRVN N-Channel On-Resistance
V
FBN
= 150mV 20 k
FBN Fault Trip Level Rising edge
700
mV
Negative Charge-Pump Soft-Start
Period
2
12
oscillator clock cycles in a 7-bit DAC
2.73
ms