Owner's manual

MAX5965A/MAX5965B

High-Power, Quad, Monolithic, PSE Controllers

for Power over Ethernet

______________________________________________________________________________________ 45

ADDR REGISTER NAME R/W PORT BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

RESET

STATE

MAXIM RESERVED

20h Reserved — G Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved —

21h Reserved — G Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved —

22h Reserved — G Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved —

23h Program R/W 4321 Reserved Reserved CLC_EN DET_BY OSCF_RS AC_TH[2] AC_TH[1] AC_TH[0] 0000,0000

24h High-Power Mode R/W G Reserved HP[2] HP[1] HP[0] Reserved Reserved Reserved Reserved 0000,0000

25h Reserved — G Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0000,0000

26h Reserved — G Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0000,0000

27h Reserved — G Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved —

28h Reserved — G Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved —

29h

Miscellaneous

Configuration 2

R/W 1234 Reserved Reserved Reserved Reserved Reserved Reserved IVEE[1] IVEE[0] 0000,0000

2Ah ICU T Regi ster s 1 and 2 R/W 21 Reserved ICUT2[2] ICUT2[1] ICUT2[0] Reserved ICUT1[2] ICUT1[1] ICUT1[0] 0000,0000

2Bh ICU T Regi ster s 3 and 4 R/W 43 Reserved ICUT4[2] ICUT4[1] ICUT4[0] Reserved ICUT3[2] ICUT3[1] ICUT[30] 0000,0000

CLASSIFICATION STATUS REGISTERS

2Ch Port 1 Class RO 1 Reserved Reserved CLASS1[5] CLASS1[4] CLASS1[3] CLASS1[2] CLASS1[1] CLASS1[0] 0000,0000

2Dh Port 2 Class RO 2 Reserved Reserved CLASS2[5] CLASS2[4] CLASS2[3] CLASS2[2] CLASS2[1] CLASS2[0] 0000,0000

2Eh Port 3 Class RO 3 Reserved Reserved CLASS3[5] CLASS3[4] CLASS3[3] CLASS3[2] CLASS3[1] CLASS3[0] 0000,0000

2Fh Port 4 Class RO 4 Reserved Reserved CLASS4[5] CLASS4[4] CLASS4[3] CLASS4[2] CLASS4[1] CLASS4[0] 0000,0000

CURRENT REGISTER

30h Current Port 1 (MSB) RO 1 IPD1[8] IPD1[7] IPD1[6] IPD1[5] IPD1[4] IPD1[3] IPD1[2] IPD1[1] 0000,0000

31h Current Port 1 (LSB) RO 1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved IPD1[0] 0000,0000

32h Current Port 2 (MSB) RO 2 IPD2[8] IPD2[7] IPD2[6] IPD2[5] IPD2[4] IPD2[3] IPD2[2] IPD2[1] 0000,0000

33h Current Port 2 (LSB) RO 2 Reserved Reserved Reserved Reserved Reserved Reserved Reserved IPD2[0] 0000,0000

34h Current Port 3 (MSB) RO 3 IPD3[8] IPD3[7] IPD3[6] IPD3[5] IPD3[4] IPD3[3] IPD3[2] IPD3[1] 0000,0000

35h Current Port 3 (LSB) RO 3 Reserved Reserved Reserved Reserved Reserved Reserved Reserved IPD3[0] 0000,0000

36h Current Port 4 (MSB) RO 4 IPD4[8] IPD4[7] IPD4[6] IPD4[5] IPD4[4] IPD4[3] IPD4[2] IPD4[1] 0000,0000

37h Current Port 4 (LSB) RO 4 Reserved Reserved Reserved Reserved Reserved Reserved Reserved IPD4[0] 0000,0000

Table 37. Register Summary (continued)

UV and UVLO bits of V

and V

asserted depends on the order V

and V

supplies are brought up.

A = AUTO pin state before reset.

M = MIDSPAN state before reset.

A3...0 = ADDRESS input states before reset.