Instruction Manual

MAX5945
Quad Network Power Controller
for Power-Over-LAN
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Table 30. Register Map Summary
ADDR
REGISTER
NAME
R/W PORT BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
RESET
STATE
INTERRUPTS
00h Interrupt RO G SUP_FLT TSTR_FLT IMAX_FLT CL_END DET_END LD_DISC PG_INT PE_INT 0000,0000 01h Int Mask R/W G MASK7 MASK6 MASK5 MASK4 MASK3 MASK2 MASK1 MASK0 AAA0,0A00
EVENTS
02h Power Event RO 4321 0000,0000 03h
Power Event
CoR
CoR
PG_CHG4 PG_CHG3 PG_CHG2 PG_CHG1
PWEN_
CHG4
PWEN_
CHG3
PWEN_
CHG2
PWEN_
CHG1
04h Detect Event RO 4321 0000,0000 05h
Detect Event
CoR
CoR
CL_END4 CL_END3 CL_END2 CL_END1 DET_END4 DET_END3 DET_END2 DET_END1
06h Fault Event RO 4321 0000,0000 07h
Fault Event
CoR
CoR
LD_DISC4 LD_DISC3 LD_DISC2 LD_DISC1 IMAX_FLT4 IMAX_FLT3 IMAX_FLT2 IMAX_FLT1
08h Tstart Event RO 4321 0000,0000 09h
Tstart Event
CoR
CoR
IVC4 IVC3 IVC2 IVC1 STRT_FLT4 STRT_FLT3 STRT_FLT2 STRT_FLT1
0Ah Supply Event RO 4321 0011,0101* 0Bh
Supply Event
CoR
CoR
TSD VDD_OV VDD_UV VEE UVLO VEE_OV VEE_UV OSC_FAIL VDD_UVLO
STATUS
0Ch Port 1 Status RO 1 reserved CLASS1[2] CLASS1[1] CLASS1[0] reserved
DET_ST1
[2]
DET_ST1
[1]
DET_ST1
[0]
0000,0000
0Dh Port 2 Status RO 2 reserved CLASS2[2] CLASS2[1] CLASS2[0] reserved
DET_ST2
[2]
DET_ST2
[1]
DET_ST2
[0]
0000,0000
0Eh Port 3 Status RO 3 reserved CLASS3[2] CLASS3[1] CLASS3[0] reserved
DET_ST3
[2]
DET_ST3
[1]
DET_ST3
[0]
0000,0000
0Fh Port 4 Status RO 4 reserved CLASS4[2] CLASS4[1] CLASS4[0] reserved
DET_ST4
[2]
DET_ST4
[1]
DET_ST4
[0]
0000,0000
10h Power Status RO 4321 PGOOD4 PGOOD3 PGOOD2 PGOOD1 PWR_EN4 PWR_EN3 PWR_EN2 PWR_EN1 0000,0000 11h Pin Status RO G reserved reserved A3 A2 A1 A0 MIDSPAN AUTO
00A3A2,
A1A0MA
*UV and UVLO bits of V
EE
and V
DD
asserted depend on the order V
EE
and V
DD
supplies are brought up.
A = AUTO pin state, A3..0 = ADDRESS pin states, M = MIDSPAN pin state, R = contact factory for current revision code Table 15a.