Manual
MAX5886
3.3V, 12-Bit, 500Msps High Dynamic
Performance DAC with Differential LVDS Inputs
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD
= DV
DD
= VCLK = 3.3V, AGND = DGND = CLKGND = 0, external reference, V
REFIO
= 1.25V, R
L
= 50Ω, I
OUT
= 20mA,
T
A
= T
MIN
to T
MAX
, unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characteriza-
tion. Typical values are at T
A
= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
f
OUT
= 10MHz, -12dB FS 81
f
CLK
= 100MHz
f
OUT
= 30MHz, -12dB FS 76
f
OUT
= 10MHz, -12dB FS 71
f
OUT
= 16MHz, -12dB FS,
T
A
≥ +25°C
69 76
f
OUT
= 50MHz, -12dB FS 72
f
CLK
= 200MHz
f
OUT
= 80MHz, -12dB FS 64
f
OUT
= 10MHz, -12dB FS 66
f
OUT
= 30MHz, -12dB FS 63
f
OUT
= 50MHz, -12dB FS 65
Spurious-Free Dynamic Range to
Nyquist
SFDR
f
CLK
= 500MHz
f
OUT
= 80MHz, -12dB FS 58
dBc
f
CLK
= 200MHz
f
OUT1
= 9MHz, -6dB FS,
f
OUT2
= 10MHz, -6dB FS
-85
2-Tone IMD TTIMD
f
CLK
= 200MHz
f
OU T 1
= 79M H z, - 6d B FS ,
f
OU T 2
= 80M H z, - 6d B FS
-61
dBc
4-Tone IMD, 1MHz Frequency
Spacing, GSM Model
FTIMD f
CLK
= 300MHz f
OUT
= 32MHz, -12dB FS -78 dBc
Adjacent Channel Leakage
Power Ratio, 4.1MHz Bandwidth,
WCDMA Model
ACLR
f
CLK
=
184.32MHz
f
OUT
= 61.44MHz 70 dB
Output Bandwidth BW
-1dB
(Note 2) 450 MHz
REFERENCE
Internal Reference Voltage Range V
REFIO
1.12 1.22 1.32 V
Reference Voltage Drift TCO
REF
±50 ppm/°C
Reference Input Compliance
Range
V
REFIOCR
0.1 1.25 V
Reference Input Resistance R
REFIO
10 kΩ
ANALOG OUTPUT TIMING
Output Fall Time t
FALL
90% to 10% (Note 3) 375 ps
Output Rise Time t
RISE
10% to 90% (Note 3) 375 ps
Output Voltage Settling Time t
SETTLE
Output settles to 0.025% FS (Note 3) 11 ns
Output Propagation Delay t
PD
(Note 3) 1.8 ns
Glitch Energy 1 pV-s
I
OUT
= 2mA 30
Output Noise N
OUT
I
OUT
= 20mA 30
pA/√Hz
TIMING CHARACTERISTICS
Data to Clock Setup Time t
SETUP
Referenced to rising edge of clock (Note 4) -0.8 ns
Data to Clock Hold Time t
HOLD
Referenced to rising edge of clock (Note 4) 1.8 ns