User guide

MAX544/MAX545
+5V, Serial-Input, Voltage-Output, 14-Bit DACs
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ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +5V ± 5%, V
REF
= +2.5V, AGND = DGND = 0, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
TIMING CHARACTERISTICS
(V
DD
= +5V ± 5%, V
REF
= +2.5V, AGND = DGND = 0, CMOS inputs, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
Note 1: Gain Error tested at V
REF
= 2.0V, 2.5V, and 3.0V.
Note 2: R
OUT
tolerance is typically ±20%.
Note 3: Min/max range guaranteed by gain-error test. Operation outside min/max limits will result in degraded performance.
Note 4: Reference input resistance is code dependent, minimum at 8554 hex.
Note 5: Slew-rate value is measured from 0% to 63%.
Note 6: Guaranteed by design. Not production tested.
Code = FFFC hex
V
IN
= 0
Code = 0000 hex, V
REF
= 1Vp-p at 100kHz
Code = 0000 hex
Code = FFFC hex
(Note 6)
CONDITIONS
mW1.5PDPower Dissipation
mA0.3 1.1I
DD
Positive Supply Current
V4.75 5.25V
DD
Positive Supply Range
V0.40V
H
Hysteresis Voltage
pF10C
IN
Input Capacitance
mVp-p1
MHz1BWReference -3dB Bandwidth
µA±1I
IN
Input Current
V0.8V
IL
Input Low Voltage
V2.4V
IH
Input High Voltage
Reference Feedthrough
dB83SNRSignal-to-Noise Ratio
75
pF
120
C
IN
Reference Input Capacitance
UNITSMIN TYP MAXSYMBOLPARAMETER
MAX545 (Note 6)
MAX545
(Note 6)
CONDITIONS
µs20
V
DD
High to CS Low
(power-up delay)
ns45t
CL
SCLK Pulse Width Low
ns45t
CH
MHz10f
SCLK
SCLK Frequency
SCLK Pulse Width High
ns50t
LDACS
CS High to LDAC Low Setup
ns50t
LDAC
LDAC Pulse Width
ns0t
DH
DIN to SCLK High Hold
ns40t
DS
DIN to SCLK High Setup
ns45t
CSS0
CS Low to SCLK High Setup
ns45t
CSS1
CS High to SCLK High Setup
ns30t
CSH0
SCLK High to CS Low Hold
ns45t
CSH1
SCLK High to CS High Hold
UNITSMIN TYP MAXSYMBOLPARAMETER
DYNAMIC PERFORMANCE—REFERENCE SECTION
STATIC PERFORMANCE—DIGITAL INPUTS
POWER SUPPLY