Manual

MAX500
CMOS, Quad, Serial-Interface
8-Bit DAC
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS—Dual Supplies (continued)
(V
DD
= +11.4V to +16.5V, V
SS
= -5V ±10%, AGND = DGND = 0V, V
REF
= +2V to (V
DD
- 4V), T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
Outputs unloaded
V
OUT
= 10V
Outputs unloaded
(Note 5)
(Note 5)
TA = +25°C (Note 2)
To ±1/2LSB, V
REF
= 10V, V
DD
= +15V,
2kΩ in parallel with 100pF load (Note 2)
For specified performance
CONDITIONS
ns150t
LDS
LOAD Delay from SCL
ns150t
LDW
LOAD Pulse Width
ns350t
2
SCL Low Time
ns350t
1
SCL High Time
ns150t
S1
SDA Valid to SCL Setup
ns150t
S1
SDA Valid to SCL Setup
mA
-10
I
SS
Negative Supply Current
-9
mA
12
I
DD
Positive Supply Current
10
V11.4 16.5V
DD
Positive Supply Voltage
kΩ2Output Load Resistance
nV-s50Digital Crosstalk
nV-s50Digital Feedthrough
38Voltage Output Slew Rate
µs2.5 4.5V
OUT
Settling Time
UNITSMIN TYP MAXSYMBOLPARAMETER
LDAC Pulse Width
t
LDAC
150 ns
SRO Output Delay t
D1
C
LOAD
= 50pF 150 ns
SCL High Time t
1
350 ns
SDA Valid to SCL Hold t
H
0 ns
LDAC Pulse Width
t
LDAC
150 ns
SCL Valid to SDA Setup t
S1
Start condition 150 ns
SDA Valid to SCL Setup t
S2
Stop condition 100 ns
T
A
= +25°C
T
A
= +25°C
V/µs
SDA Valid to Rising SCL t
S3
125 ns
SRO Output Delay t
D1
C
LOAD
= 50pF 150 ns
SCL High Time t
1
350 ns
SCL Fall Time (Note 7) 50 µs
SCL Rise Time (Note 7) 50 µs
SCL Low Time t
2
350 ns
T
A
= T
MIN
to T
MAX
T
A
= T
MIN
to T
MAX
For specified performance V11.4 16.5V
DD
Positive Supply Voltage
(Note 7) µs50SCL Rise Time
(Note 7) µs50SCL Fall Time
ns0t
H
SDA Valid to SCL Hold
DYNAMIC PERFORMANCE
POWER SUPPLIES
SWITCHING CHARACTERISTICS (T
A
= +25°C, Note 6)
3-Wire Mode
2-Wire Mode