User Manual

MAX3673
Low-Jitter Frequency Synthesizer
with Selectable Input Reference
14 ______________________________________________________________________________________
150Ω
Z = 50Ω
Z = 50Ω
150Ω
LVPECLLVPECL
50Ω
50Ω
0.1μF
0.1μF
+3.3V+3.3V
0.1μF
Figure 8. AC-Coupled LVPECL Termination
TOP VIEW
THIN QFN
(8mm
× 8mm × 0.8mm)
42 GNDIN0FAIL 1
41 V
CC
RSVD1 2
40 OUTA2RSVD2 3
39 OUTA2REFCLK0 4
38 OUTA3REFCLK0 5
37 OUTA3DM 6
36 OUTA_ENV
CC
7
35 OUTB_ENGND 8
34 OUTB4MR 9
33 OUTB4REFCLK1 10
32 OUTB3REFCLK1 11
31 OUTB3SEL_CLK 12
30 V
CC
VCC_VCO 13
29 GNDGND 14
15
56
CPLL IN1FAIL
16
55
CREG LOCK
17
54
FB_SEL RSVD4
18
53
FB_IN GND
19
52
FB_IN V
CC
20
51
OUTB0 RSVD3
21
50
OUTB0 PLL_BYPASS
22
49
V
CC
V
CC
23
48
GND GND
24
47
OUTB1 OUTA0
25
46
OUTB1 OUTA0
26
45
OUTB2 OUTA1
27
44
OUTB2 OUTA1
28
43
DB DA
EP*
*THE EXPOSED PAD OF THE TQFN PACKAGE MUST BE SOLDERED TO GROUND FOR PROPER THERMAL AND
ELECTRICAL OPERATION.
MAX3673
Pin Configuration