Manual

MAX1778/MAX1880–MAX1885
Quad-Output TFT LCD DC-DC
Converters with Buffer
26 ______________________________________________________________________________________
where η is the efficiency, f
OSC
is the oscillator frequen-
cy (see Electrical Characteristics), and I
MAIN
includes
the primary load current and the input supply currents
for the charge pumps (see Charge-Pump Input Power
and Efficiency Considerations), linear regulator, and
VCOM buffer. Considering the typical application cir-
cuit, the maximum average DC load current
(I
MAIN(MAX)
) is 300mA with an 8V output. Based on the
above equations and assuming 85% efficiency, the
inductance value is then chosen to be 4.7µH.
The inductors saturation current rating should exceed
the peak inductor current throughout the normal operat-
ing range. The peak inductor current is then given by:
Under fault conditions, the inductor current may reach
up to 1.85A (I
LIM(MAX)
), see Electrical Characteristics).
However, the controllers fast current-limit circuitry
allows the use of soft-saturation inductors while still pro-
tecting the IC.
The inductors DC resistance may significantly affect
efficiency due to the power loss in the inductor. The
power loss due to the inductors series resistance (P
LR
)
may be approximated by the following equation:
where R
L
is the inductors series resistance. For best per-
formance, select inductors with resistance less than the
internal N-channel MOSFET on-resistance (0.35 typ).
Use inductors with a ferrite core or equivalent. To mini-
mize radiated noise in sensitive applications, use a
shielded inductor.
Output Capacitor
Output capacitor selection depends on circuit stability
and output voltage ripple. A 10µF ceramic capacitor
works well in most applications (Tables 1 and 2).
Additional feedback compensation is required (see
Feedback Compensation) to increase the margin for
stability by reducing the bandwidth further. In cases
where the output capacitance is sufficiently large, addi-
tional feedback compensation will not be necessary.
Output voltage ripple has two components: variations in
the charge stored in the output capacitor with each LX
pulse, and the voltage drop across the capacitors
equivalent series resistance (ESR) caused by the cur-
rent into and out of the capacitor:
where I
PEAK
is the peak inductor current (see Inductor
Selection). For ceramic capacitors, the output voltage
ripple is typically dominated by V
RIPPLE(C)
. The voltage
rating and temperature characteristics of the output
capacitor must also be considered.
Feedback Compensation
For stability, add a pole-zero pair from FB to GND in the
form of a compensation resistor (R
COMP
) in series with
a compensation capacitor (C
COMP
) as shown in Figure
2. Select R
COMP
to be half the value of R2, the low-side
feedback resistor.
Integrator Capacitor
The MAX1778/MAX1880MAX1885 contain an internal
current integrator that improves the DC load regulation
but increases the peak-to-peak transient voltage (see
the load-transient waveforms in the Typical Operating
Characteristics). For highly accurate DC load regula-
tion, enable the current integrator by connecting a
470pF (ƒ
OSC
= 1MHz)/1000pF (ƒ
OSC
= 500kHz)
capacitor to INTG. To minimize the peak-to-peak tran-
sient voltage at the expense of DC regulation, disable
the integrator by connecting INTG to REF. When using
the MAX1883/MAX1884/MAX1885, connect a 100k
resistor to GND when disabling the integrator.
Input Capacitor
The input capacitor (C
IN
) in step-up designs reduces
the current peaks drawn from the input supply and
reduces noise injection. The value of C
IN
is largely
determined by the source impedance of the input sup-
ply. High source impedance requires high input capac-
itance, particularly as the input voltage falls. Since
step-up DC-DC converters act as constant-power
loads to their input supply, input current rises as input
voltage falls. A good starting point is to use the same
capacitance value for C
IN
as for C
OUT
.
VV V
V I R AND
V
VV
V
I
Cf
RIPPLE RIPPLE C RIPPLE ESR
RIPPLE ESR PEAK ESR COUT
RIPPLE C
MAIN IN
MAIN
MAIN
OUT OSC
,
() ( )
() ( )
()
=+
PR
IXV
V
LR L
MAIN MAIN
IN
2
I
IV
V
LIR
PEAK
MAIN MAX MAIN
IN MIN
()
()
=
+
1
2
1
η