Instruction Manual

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General Description

The MAX1510 DDR linear regulator sources and sinks up

to 3A peak (typ) using internal n-channel MOSFETs. This

linear regulator delivers an accurate 0.5V to 1.5V output

from a low-voltage power input (V

= 1.1V to 3.6V). The

MAX1510 uses a separate 3.3V bias supply to power the

control circuitry and drive the internal n-channel

MOSFETs.

The MAX1510 provides current and thermal limits to

prevent damage to the linear regulator. Additionally,

the MAX1510 generates a power-good (PGOOD) signal

to indicate that the output is in regulation. During start-

up, PGOOD remains low until the output is in regulation

for 2ms (typ). The internal soft-start limits the input

surge current.

The MAX1510 powers the active-DDR termination bus

that requires a tracking input reference. The MAX1510

can also be used in low-power chipsets and graphics

processor cores that require dynamically adjustable

output voltages. The MAX1510 is available in a 10-pin

3mm x 3mm thin DFN package.

Applications

Notebook/Desktop Computers

DDR Memory Termination

Active Termination Buses

Graphics Processor Core Supplies

Chipset/RAM Supplies as Low as 0.5V

Features

♦ Internal Power MOSFETs with Current Limit (3A typ)

♦ Fast Load-Transient Response

♦ External Reference Input with Reference

Output Buffer

♦ 1.1V to 3.6V Power Input

♦ ±15mV (max) Load-Regulation Error

♦ Thermal Fault Protection

♦ Shutdown Input

♦ Power-Good Window Comparator with 2ms

(typ) Delay

♦ Small, Low-Profile 10-Pin 3mm x 3mm TDFN

Package

♦ Ceramic or Polymer Output Capacitors

MAX1510

Low-Voltage DDR Linear Regulator

________________________________________________________________ Maxim Integrated Products 1

Ordering Information

OUT

OUTS

AGND

PGND

OUT

= V

(1.1V TO 3.6V)

BIAS

(2.7V TO 3.6V)

DDQ

(2.5V OR 1.8V)

REFOUT

= V

TTR

REFOUT

MAX1510

PGOOD

SHDN

REFIN

Typical Operating Circuit

19-3279; Rev 0; 5/04

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

PART TEMP RANGE

PIN-

PACKAGE

TOP

MARK

MAX1510ETB -40°C to +85°C

10 TDFN

(3mm x 3mm)

ABD

SHDN

OUTSPGOOD

OUT

PGND

AGND

REFIN

TDFN

3mm x 3mm

TOP VIEW

1 INREFOUT

MAX1510

Pin Configuration

Summary of content (13 pages)

PAGE 1
9-3279; Rev 0; 5/04 KIT ATION EVALU E L B A AVAIL Low-Voltage DDR Linear Regulator Features The MAX1510 DDR linear regulator sources and sinks up to 3A peak (typ) using internal n-channel MOSFETs. This linear regulator delivers an accurate 0.5V to 1.5V output from a low-voltage power input (VIN = 1.1V to 3.6V). The MAX1510 uses a separate 3.3V bias supply to power the control circuitry and drive the internal n-channel MOSFETs.
PAGE 2
MAX1510 Low-Voltage DDR Linear Regulator ABSOLUTE MAXIMUM RATINGS IN to PGND...............................................................-0.3V to +4V OUT to PGND ..............................................-0.3V to (VIN + 0.3V) OUTS to AGND ............................................-0.3V to (VIN + 0.3V) VCC to AGND............................................................-0.3V to +4V REFIN, REFOUT, SHDN, PGOOD to AGND ..-0.3V to (VCC + 0.3V) PGND to AGND ............................................
PAGE 3
Low-Voltage DDR Linear Regulator (VIN = 1.8V, VCC = 3.3V, VREFIN = VOUTS = 1.25V, SHDN = VCC, circuit of Figure 1, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS REFERENCE REFIN Voltage Range VREFIN 0.5 1.5 V REFIN Input Bias Current IREFIN -1 +1 µA 0.35 0.45 V VREFIN VREFIN +0.
PAGE 4
Typical Operating Characteristics (Circuit of Figure 1. TA = +25°C, unless otherwise noted) 1.275 VIN = 1.5V VOUT (V) 0.90 VIN = 1.8V 1.250 0.88 1.225 VIN = 1.2V 0.86 0.84 -2 -1 0 1 2 3 -3 -2 -1 0 1 2 1.0 3 2.0 MAX1510 toc03 2.5 3.0 BIAS CURRENT (ICC) vs. LOAD CURRENT (IOUT) 0.9 0.8 VOUT = 1.25V 1.0 ICC (mA) 0.5 0.3 0.4 INPUT UVLO 0.0 2.0 2.5 3.0 0.0 3.5 0.5 1.0 1.5 0.0 2.0 2.5 VIN (V) POWER GROUND CURRENT (IPGND) vs.
PAGE 5
Low-Voltage DDR Linear Regulator REFOUT VOLTAGE ERROR vs. REFOUT LOAD CURRENT STARTUP WAVEFORM 15 REFOUT VOLTAGE ERROR (mV) MAX1510 toc11 MAX1510 toc10 20 5V SHDN 0V 10 1.25V 5 VOUT 0V 0 -5 4V -10 PGOOD -15 0V -20 -10 -5 0 5 10 500µs/div REFOUT LOAD CURRENT (mA) SHUTDOWN WAVEFORM MAX1510 toc12 RLOAD = 100Ω SOURCE LOAD TRANSIENT MAX1510 toc13 5V SHDN 0V 2V VOUT AC-COUPLED 1mV/div 1V VOUT 0V 4V PGOOD 1A 0V IOUT 0A 100µs/div 20.
PAGE 6
Typical Operating Characteristics (continued) (Circuit of Figure 1. TA = +25°C, unless otherwise noted) DYNAMIC OUTPUT-VOLTAGE TRANSIENT DYNAMIC OUTPUT-VOLTAGE TRANSIENT MAX1510 toc16 MAX1510 toc17 VIN = 1.5V VOUTADJ 1.8V 1.2V VREFOUT 1.2V VREFOUT 0.9V 1.2V 0.9V 1.2V VOUT VOUT 0.9V 0.9V SINK CURRENT-LIMIT DISTRIBUTION SOURCE CURRENT-LIMIT DISTRIBUTION SAMPLE PERCENTAGE (%) 40 SAMPLE SIZE = 200 30 20 MAX1510 toc19 +85°C 50 MAX1510 toc18 +25°C 2.5V VOUTADJ 1.8V 20.
PAGE 7
Low-Voltage DDR Linear Regulator PIN NAME FUNCTION 1 REFOUT 2 VCC 3 AGND Analog Ground. Connect the backside pad to AGND. 4 REFIN External Reference Input. REFIN sets the output regulation voltage (VOUTS = VREFIN). 5 PGOOD 6 OUTS Output Sense Input. The OUTS regulation level is set by the voltage at REFIN. Connect OUTS to the remote DDR termination bypass capacitors. OUTS is internally connected to OUT through a 12kΩ resistor. 7 SHDN Shutdown Control Input.
PAGE 8
MAX1510 Low-Voltage DDR Linear Regulator 3.3V BIAS SUPPLY VCC IN EN UVLO OFF ON INPUT 1.1V TO 3.6V SOFTSTART SHDN THERMAL SHDN REFIN VDDQ OUT Gm PGND VTTR 12kΩ REFOUT OUTS AGND REFIN +150mV EN 8Ω REFIN -150mV POWERGOOD PGOOD MAX1510 DELAY LOGIC Figure 2.
PAGE 9
Low-Voltage DDR Linear Regulator 3.3V Bias Supply (VCC) The VCC input powers the control circuitry and provides the gate drive to the pass transistor. This improves efficiency by allowing VIN to be powered from a lower supply voltage. Power V CC from a well-regulated 3.3V supply. Current drawn from the VCC supply remains relatively constant with variations in VIN and load current. Bypass VCC with a 1µF or greater ceramic capacitor as close to the device as possible.
PAGE 10
MAX1510 Low-Voltage DDR Linear Regulator SHDN 200µs CURRENT LIMIT OUTPUT OVERLOAD CONDITION POWER-GOOD WINDOW OUT 2ms STARTUP DELAY PGOOD 10µs PROPAGATION DELAY 10µs PROPAGATION DELAY Figure 3. MAX1510 PGOOD and Soft-Start Waveforms Power-Good (PGOOD) The MAX1510 provides an open-drain PGOOD output that goes high 2ms (typ) after the output initially reaches regulation during startup. PGOOD transitions low 10µs after the output goes out of regulation by ±150mV, or when the device enters shutdown.
PAGE 11
Low-Voltage DDR Linear Regulator The maximum power dissipation of the MAX1510 depends on the thermal resistance of the 10-pin TDFN package and the circuit board, the temperature difference between the die and ambient air, and the rate of airflow.
PAGE 12
MAX1510 Low-Voltage DDR Linear Regulator Noise, PSRR, and Transient Response PC Board Layout Guidelines The MAX1510 operates with low-dropout voltage and low quiescent current in notebook computers while maintaining good noise, transient response, and AC rejection specifications. Improved supply-noise rejection and transient response can be achieved by increasing the values of the input and output capacitors. Use passive filtering techniques when operating from noisy sources.
PAGE 13
Low-Voltage DDR Linear Regulator 6, 8, &10L, DFN THIN.EPS D N PIN 1 INDEX AREA E E2 DETAIL A CL CL L A L e e PACKAGE OUTLINE, 6, 8, 10 & 14L, TDFN, EXPOSED PAD, 3x3x0.80 mm 21-0137 NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY E 1 2 COMMON DIMENSIONS SYMBOL A MIN. 0.70 0.80 D 2.90 3.10 2.90 3.10 0.00 0.05 E A1 L k MAX. 0.40 0.20 0.25 MIN. A2 0.20 REF. PACKAGE VARIATIONS PKG. CODE N D2 E2 e JEDEC SPEC b [(N/2)-1] x e T633-1 6 1.50±0.10 2.30±0.10 0.