Manual

MAX1492/MAX1494
3.5- and 4.5-Digit, Single-Chip ADCs
with LCD Drivers
22 ______________________________________________________________________________________
START: Start Bit. The first 1 clocked into the
MAX1492/MAX1494 is the first bit of the
command byte.
(R/W): Read/Write. Set this bit to 1 to read from
the specified register. Set this bit to 0 to
write to the selected register. Note that
certain registers are read-only. Write com-
mands to a read-only register are
ignored.
(RS4–RS0): Register Address Bits. RS4 to RS0 specify
which register is accessed.
X: Don’t care.
MSB
LSB
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
START (1) R/W RS4 RS3 RS2 RS1 RS0 X
This register contains the status of the conversion
results.
SIGN: Latched Negative-Polarity Indicator.
Latches high when the result is negative.
Clears by reading the status register,
unless the condition remains true.
OVER: Overrange Bit. Latches high if an over-
range condition occurs (the ADC result is
larger than the value in the overrange reg-
ister). Clears by reading the status regis-
ter, unless the condition remains true.
UNDER: Underrange Bit. Latches high if an under-
range condition occurs (the ADC result is
less than the value in the underrange regis-
ter). Clears by reading the status register,
unless the condition remains true.
LOW_BATT: Low-Battery Bit. Latches high if the voltage
at the LOWBATT is lower than 2.048V (typ).
Clears by reading the status register,
unless the condition remains true.
DRDY: Data-Ready Bit. Latches high to indicate
a completed conversion result with valid
data. Read the ADC Result-Register 1 to
clear this bit.
MSB
LSB
SIGN OVER UNDER LOW_BATT DRDY 0 0 0
This register is the primary control register for the
MAX1492/MAX1494. It is a 16-bit read/write register. It
is used to indicate the desired clock and reference
source. It sets the LCD controls, range modes, power-
down modes, offset calibration, and the reset register
function (CLR).
MSB
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
SPI/ADC EXTCLK INTREF DP_EN DPSET2 DPSET1 PD_DIG PD_ANA
LSB
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
HOLD PEAK RANGE CLR SEG_SEL
OFFSET_CAL1 OFFSET_CAL2
0
Status Register (Read Only):
Control Register (Read/Write):
Command Byte (Write Only):
Default values: 0000h
Default values: 00h